56F8323 Technical Data, Rev. 17
40
Freescale Semiconductor
Preliminary
4.7 Peripheral Memory Mapped Registers
On-chip peripheral registers are part of the data memory map on the 56800E series. These locations may
be accessed with the same addressing modes used for ordinary Data memory, except all peripheral
registers should be read/written using word accesses only.
Table 4-7 summarizes base addresses for the set of peripherals on the 56F8323 and 56F8123 devices.
Peripherals are listed in order of the base address.
The following tables list all of the peripheral registers required to control or access the peripherals.
Note: Features in italics are NOT available in the 56F8123 device.
Table 4-7 Data Memory Peripheral Base Address Map Summary
Peripheral
Prefix
Base Address
Table Number
Timer A
TMRA
X:$00 F040
Timer C
TMRC
X:$00 F0C0
PWM A
PWMA
X:$00 F140
Quadrature Decoder 0
DEC0
X:$00 F180
ITCN
X:$00 F1A0
ADC A
ADCA
X:$00 F200
Temperature Sensor
TSENSOR
X:$00 F270
SCI #0
SCI0
X:$00 F280
SCI #1
SCI1
X:$00 F290
SPI #0
SPI0
X:$00 F2A0
SPI #1
SPI1
X:$00 F2B0
COP
X:$00 F2C0
PLL, OSC
CLKGEN
X:$00 F2D0
GPIO Port A
GPIOA
X:$00 F2E0
GPIO Port B
GPIOB
X:$00 F300
GPIO Port C
GPIOC
X:$00 F310
SIM
X:$00 F350
Power Supervisor
LVI
X:$00 F360
FM
X:$00 F400
FlexCAN
FC
X:$00 F800