參數(shù)資料
型號: MC56F8323MFB60
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 數(shù)字信號處理
英文描述: 0-BIT, 120 MHz, OTHER DSP, PQFP64
封裝: PLASTIC, LQFP-64
文件頁數(shù): 49/140頁
文件大?。?/td> 741K
代理商: MC56F8323MFB60
56F8323 Technical Data, Rev. 17
16
Freescale Semiconductor
Preliminary
Part 2 Signal/Connection Descriptions
2.1 Introduction
The input and output signals of the 56F8323 and 56F8123 are organized into functional groups, as
detailed in Table 2-1 and as illustrated in Figure 2-1 and Figure 2-2. In Table 2-2, each table row
describes the signal or signals present on a pin.
Table 2-1 Functional Group Pin Allocations
Functional Group
Number of Pins in Package
56F8323
56F8123
Power (VDD or VDDA)6
6
Power Option Control
1
Ground (VSS or VSSA)5
5
Supply Capacitors1 & VPP
2
1. If the on-chip regulator is disabled, the VCAP pins serve as 2.5V VDD_CORE power inputs
2. The VPP input shares the IRQA input
44
PLL and Clock
2
Interrupt and Program Control
2
Pulse Width Modulator (PWM) Ports3
3. Pins in this section can function as SPI #1 and GPIO
12
Serial Peripheral Interface (SPI) Port 04
4. Pins in this section can function as SCI #1 and GPIO
48
Quadrature Decoder Port 05
5. Alternately, can function as Quad Timer A pins or GPIO
4—
CAN Ports
2
Analog-to-Digital Converter (ADC) Ports
13
Timer Module Port C6
6. Two pins can function as SCI #0 and GPIO
Note: See Table 1-1 for 56F8123 functional differences.
33
Timer Module Port A
4
JTAG/Enhanced On-Chip Emulation (EOnCE)
5
Temperature Sensse
1
Dedicated GPIO
10
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