參數(shù)資料
型號: MC56F8323MFB60
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 數(shù)字信號處理
英文描述: 0-BIT, 120 MHz, OTHER DSP, PQFP64
封裝: PLASTIC, LQFP-64
文件頁數(shù): 62/140頁
文件大?。?/td> 741K
代理商: MC56F8323MFB60
56F8323 Technical Data, Rev. 17
28
Freescale Semiconductor
Preliminary
VREFP
37
Input/
Output
Analog Input/
Output
VREFP, VREFMID & VREFN — Internal pins for voltage reference which
are brought off-chip so that they can be bypassed. Connect to a
0.1
μF ceramic low ESR capacitor
VREFMID
36
VREFN
35
VREFLO
38
Schmitt
Input
Analog Input VREFLO — Analog Reference Voltage Low. This should normally be
connected to a low-noise VSS.
TEMP_SENSE
34
Output
Analog
Output
Temperature Sense Diode — This signal connects to an on-chip
diode that can be connected to one of the ADC inputs and used to
monitor the temperature of the die. Must be bypassed with a 0.01
μF
capacitor
CAN_RX
(GPIOC2)
61
Schmitt
Input
Schmitt
Input/
Output
Input,
pull-up
enabled
FlexCAN Receive Data — This is the CAN input. This pin has an
internal pull-up resistor.
Port C GPIO — This GPIO pin can be individually programmed as
an input or output pin.
In the 56F8323, the default state after reset is CAN_RX.
In the 56F8123, the default state is not one of the functions offered
and must be reconfigured.
CAN_TX
(GPIOC3)
62
Open
Drain
Output
Schmitt
Input/
Output
Open
Drain
Output
FlexCAN Transmit Data — CAN output with internal pull-up enable
at reset.*
* Note: If a pin is configured as open drain output mode, internal
pull-up will automatically be disabled when it outputs low. Internal
pull-up will be enabled unless it has been manually disabled by
clearing the corresponding bit in the PUREN register of the GPIO
module, when it outputs high.
If a pin is configured as push-pull output mode, internal pull-up will
automatically be disabled, whether it outputs low or high.
Port C GPIO — This GPIO pin can be individually programmed as
an input or output pin.
In the 56F8323, the default state after reset is CAN_TX.
In the 56F8123, the default state is not one of the functions offered
and must be reconfigured.
Table 2-2 Signal and Package Information for the 64-Pin LQFP
Signal Name
Pin No.
Type
State During
Reset
Signal Description
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