參數(shù)資料
型號: MC56F8323MFB60
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 數(shù)字信號處理
英文描述: 0-BIT, 120 MHz, OTHER DSP, PQFP64
封裝: PLASTIC, LQFP-64
文件頁數(shù): 114/140頁
文件大小: 741K
代理商: MC56F8323MFB60
Register Descriptions
56F8323 Technical Data, Rev. 17
Freescale Semiconductor
75
Preliminary
5.6.10.4
Reserved—Bits 9–8
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
5.6.10.5
ADC A Zero Crossing or Limit Error Interrupt Priority Level
(ADCA_ZC IPL)—Bits 7–6
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.10.6
Reserved—Bits 5–4
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
5.6.10.7
ADC A Conversion Complete Interrupt Priority Level
(ADCA_CC IPL)—Bits 3–2
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.10.8
Reserved—Bits 1–0
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
5.6.11
Vector Base Address Register (VBA)
Figure 5-13 Vector Base Address Register (VBA)
5.6.11.1
Reserved—Bits 15–13
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
Base + $A
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Read
0
VECTOR BASE ADDRESS
Write
RESET
00000
0000000
0000
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