參數(shù)資料
型號(hào)： MC56F8323MFB60
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 數(shù)字信號(hào)處理
英文描述： 0-BIT, 120 MHz, OTHER DSP, PQFP64
封裝： PLASTIC, LQFP-64
文件頁數(shù)： 100/140頁
文件大?。?/td> 741K
代理商： MC56F8323MFB60
56F8323 Technical Data, Rev. 17
62
Freescale Semiconductor
Preliminary
5.6.1
Interrupt Priority Register 0 (IPR0)
Figure 5-3 Interrupt Priority Register 0 (IPR0)
5.6.1.1
Reserved—Bits 15–14
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
5.6.1.2
EOnCE Breakpoint Unit 0 Interrupt Priority Level (BKPT_U0 IPL)—
Bits13–12
This field is used to set the interrupt priority levels for IRQs. This IRQ is limited to priorities 1 through 3.
It is disabled by default.
00 = IRQ disabled (default)
01 = IRQ is priority level 1
10 = IRQ is priority level 2
11 = IRQ is priority level 3
5.6.1.3
EOnCE Step Counter Interrupt Priority Level (STPCNT IPL)—
Bits 11–10
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 1 through 3.
It is disabled by default.
00 = IRQ disabled (default)
01 = IRQ is priority level 1
10 = IRQ is priority level 2
11 = IRQ is priority level 3
5.6.1.4
Reserved—Bits 9–0
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
5.6.2
Interrupt Priority Register 1 (IPR1)
Figure 5-4 Interrupt Priority Register 1 (IPR1)
Base + $0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Read
0
BKPT_U0 IPL
STPCNT IPL
0
Write
RESET
0
000
Base + $1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Read
0
RX_REG IPL
TX_REG IPL
TRBUF IPL
Write
RESET
0
000000
00
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