參數(shù)資料
型號: MC56F8323MFB60
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 數(shù)字信號處理
英文描述: 0-BIT, 120 MHz, OTHER DSP, PQFP64
封裝: PLASTIC, LQFP-64
文件頁數(shù): 58/140頁
文件大?。?/td> 741K
代理商: MC56F8323MFB60
56F8323 Technical Data, Rev. 17
24
Freescale Semiconductor
Preliminary
MISO0
(RXD1)
(GPIOB1)
22
Schmitt
Input/
Output
Schmitt
Input
Schmitt
Input/
Output
Input,
pull-up
enabled
SPI 0 Master In/Slave Out — This serial data pin is an input to a
master device and an output from a slave device. The MISO line of a
slave device is placed in the high-impedance state if the slave device
is not selected. The slave device places data on the MISO line a
half-cycle before the clock edge the master device uses to latch the
data.
Receive Data — SCI1 receive data input
Port B GPIO — This GPIO pin can be individually programmed as
an input or output pin.
After reset, the default state is MISO0.
SS0
(TXD1)
(GPIOB0)
21
Schmitt
Input
Output
Schmitt
Input/
Output
Input,
pull-up
enabled
SPI 0 Slave Select — SS0 is used in slave mode to indicate to the
SPI module that the current transfer is to be received.
Transmit Data — SCI1 transmit data output
Port B GPIO — This GPIO pin can be individually programmed as
an input or output pin.
After reset, the default state is SS0.
PWMA0
(GPIOA0)
3
Output
Schmitt
Input/
Output
In reset,
output is
disabled,
pull-up is
enabled
PWMA0 — This is one of six PWMA output pins.
Port A GPIO — This GPIO pin can be individually programmed as
an input or output pin.
In the 56F8323, the default state after reset is PWMA0.
In the 56F8123, the default state is not one of the functions offered
and must be reconfigured.
PWMA1
(GPIOA1)
4
Output
Schmitt
Input/
Output
In reset,
output is
disabled,
pull-up is
enabled
PWMA1 — This is one of six PWMA output pins.
Port A GPIO — This GPIO pin can be individually programmed as
an input or output pin.
In the 56F8323, the default state after reset is PWMA1.
In the 56F8123, the default state is not one of the functions offered
and must be reconfigured
Table 2-2 Signal and Package Information for the 64-Pin LQFP
Signal Name
Pin No.
Type
State During
Reset
Signal Description
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