參數(shù)資料
型號： MC56F8323MFB60
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 數(shù)字信號處理
英文描述： 0-BIT, 120 MHz, OTHER DSP, PQFP64
封裝： PLASTIC, LQFP-64
文件頁數(shù)： 6/140頁
文件大小： 741K
代理商： MC56F8323MFB60
Configuration
56F8323 Technical Data, Rev. 17
Freescale Semiconductor
103
Preliminary
Table 8-3 GPIO External Signals Map
GPIO Function
Peripheral
Function
Package
Pin
Notes
GPIOA0
PWMA0
3
PWM is NOT available in 56F8123
GPIOA1
PWMA1
4
PWM is NOT available in 56F8123
GPIOA2
PWMA2 / SSI
7
SIM register SIM_GPS is used to select between SPI1 and
PWMA on a pin-by-pin basis
PWM is NOT available in 56F8123
GPIOA3
PWMA3 / MISO1
8
SIM register SIM_GPS is used to select between SPI1 and
PWMA on a pin-by-pin basis
PWM is NOT available in 56F8123
GPIOA4
PWMA4 / MOSI1
9
SIM register SIM_GPS is used to select between SPI1 and
PWMA on a pin-by-pin basis
PWM is NOT available in 56F8123
GPIOA5
PWMA5 / SCLK1
10
SIM register SIM_GPS is used to select between SPI1 and
PWMA on a pin-by-pin basis
PWM is NOT available in 56F8123
GPIOA6
FAULTA0
13
GPIOA7
FAULTA1
14
GPIOA8
FAULTA2
15
GPIOA9
ISA0
16
GPIOA10
ISA0
18
GPIOA11
ISA2
19
GPIOB0
SS0 / TXD1
21
SIM register SIM_GPS is used to select between SPI1 and
PWMA on a pin-by-pin basis
GPIOB1
MISO0 / RXD1
22
SIM register SIM_GPS is used to select between SPI1 and
PWMA on a pin-by-pin basis
GPIOB2
MOSI0
24
GPIOB3
SCLK0
25
GPIOB4
HOME0 / TA3
49
Quad Decoder 0 register DECCR is used to select between
Decoder 0 and Timer A
Quad Decoder is NOT available in 56F8123
GPIOB5
INDEX0 / TA2
50
Quad Decoder 0 register DECCR is used to select between
Decoder 0 and Timer A
Quad Decoder is NOT available in 56F8123
GPIOB6
PHASEB0 / TA1
51
Quad Decoder 0 register DECCR is used to select between
Decoder 0 and Timer A
Quad Decoder is NOT available in 56F8123
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