參數(shù)資料
型號： MC56F8323MFB60
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 數(shù)字信號處理
英文描述： 0-BIT, 120 MHz, OTHER DSP, PQFP64
封裝： PLASTIC, LQFP-64
文件頁數(shù)： 15/140頁
文件大?。?/td> 741K
代理商： MC56F8323MFB60
DC Electrical Characteristics
56F8323 Technical Data, Rev. 17
Freescale Semiconductor
111
Preliminary
10.2.1
Voltage Regulator Specifications
The 56F8323/56F8123 have two on-chip regulators. One supplies the PLL and has no external pins;
therefore, it has no external characteristics which must be guaranteed (other than proper operation of the
device). The second regulator supplies approximately 2.6V to the device’s core logic. This regulator
requires two external 2.2μF, or greater, capacitors for proper operation. Ceramic and tantalum capacitors
tend to provide better performance tolerances. The output voltage can be measured directly on the VCAP
pins. The specifications for this regulator are shown in Table 10-9.
Table 10-8 Current Consumption per Power Supply Pin (Typical)
On-Chip Regulator Disabled (OCR_DIS = High)
Mode
IDD_Core
IDD_IO
1
1. No Output Switching (Output switching current can be estimated from I = CVf for each output)
IDD_ADC
IDD_OSC_PLL
Test Conditions
RUN1_MAC
110mA
13
μA25mA
2.5mA
60MHz Device Clock
All peripheral clocks are enabled
Continuous MAC instructions with
fetches from Data RAM
ADC powered on and clocked
Wait3
55mA
13
μA35μA2.5mA
60MHz Device Clock
All peripheral clocks are enabled
ADC powered off
Stop1
700
μA13μA0μA360μA
4MHz Device Clock
All peripheral clocks are off
Relaxation oscillator is on
ADC powered off
PLL powered off
Stop2
100
μA13μA0μA145μA
Relaxation oscillator is off
All peripheral clocks are off
ADC powered off
PLL powered off
Table 10-9. Regulator Parameters
Characteristic
Symbol
Min
Typical
Max
Unit
Unloaded Output Voltage
(0mA Load)
VRNL
2.25
—
2.75
V
Loaded Output Voltage
(200mA load)
VRL
2.25
—
2.75
V
Line Regulation @ 250mA load
(VDD33 ranges from 3.0V to 3.6V)
VR
2.25
—
2.75
V
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