參數(shù)資料
型號(hào)： MC44011FN
廠商： MOTOROLA INC
元件分類： 消費(fèi)家電
英文描述： BUS CONTROLLED MULTISTANDARD VIDEO PROCESSOR
中文描述： SPECIALTY CONSUMER CIRCUIT, PQCC44
封裝： PLASTIC, LCC-44
文件頁(yè)數(shù)： 48/52頁(yè)
文件大?。?/td> 835K
代理商： MC44011FN
MC44011
APPENDIX D
48
MOTOROLA ANALOG IC DEVICE DATA
PLL Loop Theory
High Frequency Line–Locked Clock Generator
This section is not intended as a complete loop theory, its
aim is merely to point out the idiosyncrasies of the loop, and
provide the user with enough information for the selection of
filter components. For a more in depth explanation, the
references at the end of this section may be consulted.
Figure D1. PLL2 Basic Configuration
Frequency
Divider
15.7 kHz
Phase and
Frequency
Comparator
15.7 kHz
from PLL1
Down
Up
15 k
Return
Pixel
Clock
VCO
Charge
Pump
15
PLL2 Filter
C2
C1
R
18
16
The following general remarks apply to the loop (PLL2):
– The loop frequency is
≈
15.7 kHz.
– In spite of the samples nature of the loop, a continuous
time approximation is possible if the loop bandwidth is
sufficiently small.
– Ripple on VC (filter pin) is a function of loop bandwidth.
– The loop is a type II, 3rd order. However, since C2 is
small, the pole it creates is far removed from the low
frequency dominant poles, and the loop can be analyzed
as a 2nd order loop.
The following remarks apply to the Phase and Frequency
Comparator:
– Phase and frequency sensitive.
– Independent of duty cycle.
– It has 3 allowed states: up, down, and off (high
impedance).
– The VCO is always pulled in the right direction during
acquisition.
– The Comparator’s gain is higher at or near lock.
The last two remarks imply that only the higher value need
be taken into account, as acquisition will be slower but
always in the correct direction, whereas the higher gain will
come into action as soon as the error reaches 2
π
.
The following values are selected and defined:
C2 = C1/10 or less, to satisfy the requirement that the effect
of C2 on the low frequency response of the loop be minimal,
and similar to a 2nd order loop.
ξ
ω
i
τ
K
K
′
Ko
= 70 x 106 rad/V
Stability analysis with C2 = C1/10 and K
′
= 2 (
ξ
= 0.707)
gives a minimum value of 7.5 for the ratio
ω
i/K. To have some
margin, a reasonable value can be 15 to 20 or higher.
Selecting
ω
i/K = 20 yields,
K =
ω
i/20
≈
5000.
Using the following items:
K
′
= 2,
τ
=
2/K = 400
μ
s,
K = Ko x Ip x R/(2
π
N)
Ip = 20
μ
A
N = 2000 (average value)
yields a value of 22 k
for R. Using a value of 400
μ
s for
τ
, C1
calculates to 18 nF, and C2 calculates to 1.8 nF.
With the above values, the loop’s natural frequency
(
ω
n),
and loop bandwidth (
ω
3dB) can be calculated:
ω
n = {(Ko/N) x Ip/(2
π
C) }0.5 = 3520 rad/sec.
fn = 3520/2
π
= 560 Hz.
ω
3dB
≈
2 x
ω
n = 1120 Hz (valid if
ξ
= 0.707).
= 0.707 (damping factor).
= 15750 x 2p = 98960 rad/sec (input frequency).
= RC as the loop filter
= Ko x Ip x R/(2
π
N) – the loop gain
= K x
τ
= 4
ξ
2 (the normalized loop gain)
The circuit designer should be cautioned at this point that
the above calculated values are not necessarily optimum for
every application. Besides the fact that several assumptions
were made in the discussion, the equations cannot account
for items such as the PC board layout, characteristics of the
external divider, and noise from various sources. The above
calculated values provide for a functional circuit, which
should then be tweaked to obtain minimum jitter at the pixel
clock output.
When initially adjusting the filter component values, it
is advisable to maintain the same general time constant
(400
μ
s in this example), and the same x10 relationship
between C1 and C2.
References:
(1) Charge–Pump Phase–Lock–Loopsby Floyd M. Gardner, IEEE Transactions on Communications, Vol. com–28, no. 11, Nov. 1980.
(2) Phaselock Techniquesby Floyd M. Gardner, J. Wiley & Sons, 1979.
(3) Phase–Locked–Loopsby Roland E. Best, McGraw Hill, 1984.
(4) AN–535, Phase–Locked–Loop Design Fundamentals Motorola.
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