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參數(shù)資料
| 型號： | MC44011FN |
| 廠商： | MOTOROLA INC |
| 元件分類： | 消費家電 |
| 英文描述： | BUS CONTROLLED MULTISTANDARD VIDEO PROCESSOR |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁數(shù)： | 34/52頁 |
| 文件大?。?/td> | 835K |
| 代理商： | MC44011FN |
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MC44011
34
MOTOROLA ANALOG IC DEVICE DATA
Table 14. Control Bit Description
Control Bit
Name
Description
$77–7
S–VHS–Y
Set to 0 for normal Composite Video inputs at V1 and/or V2 (Pins 1, 3). Set to 1 for S–VHS (YC)
operation. When 1, the Y–input at the selected video input (V1 or V2, selected by Bit $88–7)
bypasses the initial luma delay line, and associated luma/chroma filters and peaking. The signal
passes through the second luma delay, adjustable with Bits D1–D3. Luma is output at Pin 33.
$77–6
S–VHS–C
Set to 0 for normal Composite Video inputs at V1 and/or V2 (Pins 1, 3). Set to 1 for S–VHS (YC)
operation. When 1, the chroma input at the non–selected video input (V1 or V2 by Bit $88–7) is
directed to the ACC loop and PAL/NTSC detector. Color difference signals are then output at
Pins 41 and 42.
$77–5
FSI
Set to 0 for a Vertical Sync output rate of 50 Hz. Set to 1 for 100 Hz. Useable in PAL systems only.
$77–4
L2 GATE
When set to 0, the pixel clock charge pump (PLL2) operation is inhibited during the Vertical
Retrace to minimize momentary instabilities. When set to 1, PLL2 operation is not inhibited.
$77–3
BLCP GATE
When 0, Vertical Gating of the black level clamp pulse during the Vertical Retrace occurs to
minimize momentary instabilities. The Vertical Gating can be inhibited by setting this bit to 1.
$77–2
L1 GATE
When set to 0, the horizontal PLL’s phase detector (PLL1) operation is inhibited during the Vertical
Retrace to minimize momentary instabilities. When set to 1, the phase detector is not inhibited. If
PLL1 gain is high (Bit $83–6 = 1), gating cannot be enabled.
$77–1, 0
CB1, CA1
Sets the Vertical Timebase operating method according to Table 10.
$78–7
36/68
μ
s
When 0, the time delay from the sync polarity reversal within the Composite Sync to the leading
edge of the Vertical Sync output (Pin 4) is 36
μ
s. When 1, the time delay is 68
μ
s.
(See Figure 33 and 34).
$78–6
CalKill
When 0, the Horizontal Calibration Loop is enabled for two lines (lines 4 and 5) in each field.
When 1, the Calibration Loop is not engaged. Upon power–up, this bit is ineffective (Calibration
Loop is enabled) until bit $86–6 is set to 0, and register $00 is set to $00.
$79–7
HI
This bit is not used in the MC44011, and must be set to 1.
$79–6
VI
This bit is not used in the MC44011, and must be set to 1.
$7A–7
Xtal
When 0, the crystal at Pin 38 (17.7 MHz) is selected. When 1, the crystal at Pin 36 (14.3 MHz)
is selected.
$7A–6
SSD
This bit is not used in the MC44011, and must be set to 0.
$7B–7, 6
T1, T2
Used to set the Sound Trap Notch filter frequency according to Table 3.
$7C–7, 6 $7D–6
SSC, SSA, SSB
Sets the NTSC/PAL decoder to the correct system according to Table 4.
$7D–7 $7E–7, 6
P1, P2, P3
Sets the Luma Peaking in the decoder section according to Table 5. (See text).
$7F–7, 6 $80–6
D3, D1, D2
Sets the Luma Delay in the decoder section according to Table 6. (See text).
$80–7
RGB EN
When 0, permits the RGB inputs (Pins 26 to 28) to be selected with the Fast Commutate (FC)
input (Pin 25). When 1, the FC input is disabled, preventing the RGB inputs from being selected.
When the RGB inputs are selected, the Color Difference inputs (Pins 30, 31) are deselected.
$81–7
Y2 EN
When 1, the Y2 Luma input (Pin 29) is selected. When 0, it is deselected.
$81–6
Y1 EN
When 1, the Y1 Luma Signal (provided by the decoder section to the color difference section) is
selected. When 0, it is deselected.
$82–7
YUV EN
When 0, Pins 20 to 22 provide RGB output signals. When 1, those pins provide YUV
output signals.
$82–6
YX EN
Effective only when the RGB inputs are selected. When 0, the RGB inputs (Pins 26 to 28) are
directed to the RGB outputs (Pins 20 to 22) via the Contrast and Brightness controls. When 1, the
RGB inputs are directed through the Color Difference Matrix, allowing Saturation control in
addition to the Brightness and Contrast controls. See Figure 36.
$83–7
L2 Gain
When 0, the gain of the pixel clock VCO (PLL2) is high (50
μ
A). When 1, the gain is low (20
μ
A).
$83–6
L1 Gain
When 0, the Horizontal Phase Detector Gain (PLL1) is low. When 1, the gain is high.
$84–7
H Switch
When 0, Pin 12 is open. When 1, Pin 12 is internally switched to ground, allowing the PLL1 filter
operation to be adjusted for noisy signals.
$85–7
PClk/2
When 0, the PLL2 VCO provides the Pixel Clock at Pin 18 directly. When 1, the VCO output is
directed through a
÷
2 stage, and then to Pin 18.
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