參數(shù)資料
型號(hào)： MC44011FN
廠商： MOTOROLA INC
元件分類(lèi)： 消費(fèi)家電
英文描述： BUS CONTROLLED MULTISTANDARD VIDEO PROCESSOR
中文描述： SPECIALTY CONSUMER CIRCUIT, PQCC44
封裝： PLASTIC, LCC-44
文件頁(yè)數(shù)： 32/52頁(yè)
文件大?。?/td> 835K
代理商： MC44011FN
MC44011
32
MOTOROLA ANALOG IC DEVICE DATA
The Field ID output (Pin 7) indicates which field is being
processed when interlaced signals are applied, but the
polarity depends on Bit $78–7. Table 11 indicates Pin 7
output. When non–interlaced signals are being processed,
Pin 7 will be a constant high level when $78–7 is set to 1, and
will be a constant low level when $78–7 is set to a 0. Loading
on Pin 7 should not be less than 2.0 k
to either ground or
5.0 V. Figures 33 and 34 indicate the timing.
Table 11. Field ID Output
36/68
μ
s
($78–7)
Field
Field ID
(Pin 7)
1
1
High
1
2
Low
0
1
Low
0
2
High
Sync Separator
The sync separator block provides composite sync
information to the horizontal PLL, and to various other blocks
within the MC44011 from one of several sources. It also
provides composite sync output at Pin 13 when Bit $85–6 = 1.
The sync source is selectable via the I2C bus according to
Table 12.
Table 12. Sync Source
Vin Sync
($86–7)
Y2 Sync
($87–7)
RGB Sync
($88–6)
Sync Source
0
0
0
None
0
0
1
RGB (Pins 26–28)
0
1
0
Y2 (Pin 29)
1
X
X
Comp. Video (Pins 1, 3)
Setting Bit $86–7 to a 1 overrides the other bits, thereby
deriving the sync from the composite video input (either Pin 1
or 3) selected by Bit $88–7.
When RGB is selected, sync information on Pins 26 to 28
is used. Sync may be applied to all three inputs, or to any one
with the other two ac grounded. If RGB signals are applied to
these pins, sync may be present on any one or all three.
When Y2 is selected, sync information on Pin 29 is used.
The sync amplitude applied to any of the above pins must be
greater than 100 mV, and it must be capacitor coupled.
This system allows a certain amount of flexibility in using
the MC44011, in that if the sync information is not present as
part of the applied video signals, sync may be applied to
another input. In other words, the input selected for the sync
information need not be the same as the input selected for
the video information.
SOFTWARE CONTROL OF THE MC44011
I2C Interface
Communication to and from the MC44011 follows the I2C
interface arrangement and protocol defined by Philips
Corporation. In simple terms, I2C is a two line, multimaster
bidirectional bus for data transfer. See Appendix C for a
description of the I2C requirements and operation. Although
an I2C system can be multimaster, the MC44011 never
functions as a master.
The MC44011 has a write address of $8A, and a flag read
address of $8B. It requires that an external microprocessor
read the internal flags, and then set the appropriate registers.
The MC44011 does not do any automatic internal switching
when applied video signals are changed. A block diagram of
the I2C interface is shown in Figure 41. Since writing to the
MC44011’s registers can momentarily create jitter and other
undesirable artifacts on the screen, writing should be done
only during vertical retrace (before line 20). Reading of flags,
however, can be done anytime.
Sub–Address
Latches
Read/
Write
Latch
Chip
Address
Latch
Reset
Start Bit
Recognition
Clock Counter
8–Bit Shift Register
Flag Data
19 Registers
Acknowledge
Data
Clock
5
6
Figure 41. I2C Bus Interface and Decoder
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