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參數(shù)資料
| 型號： | MC44011FN |
| 廠商： | MOTOROLA INC |
| 元件分類： | 消費家電 |
| 英文描述： | BUS CONTROLLED MULTISTANDARD VIDEO PROCESSOR |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁數(shù)： | 43/52頁 |
| 文件大?。?/td> | 835K |
| 代理商： | MC44011FN |
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MC44011
43
MOTOROLA ANALOG IC DEVICE DATA
Use of the MC44145 Pixel Clock Generator
For most applications the Pixel Clock Generator (PLL2)
within the MC44011 will be suitable. In those cases, however,
where the pixel clock frequency is set to within
±
1.0 MHz of
the selected crystal frequency (14.3 MHz or 17.7 MHz), or to
within
±
1.0 MHz of double the selected crystal frequencies,
undesirable noise artifacts may be present on the RGB
outputs. In these cases the MC44145 should be used to
generate the Pixel Clock. The circuitry within the MC44145
duplicates that of the MC44011, but since it is physically
removed from the circuitry within the MC44011, the
interfering noise is not generated. If the MC44145 is used,
the Pixel Clock Generator within the MC44011 should be shut
off by setting the DAC of register $7F to 63, eliminating the
components at Pin 16, and grounding Pin 16.
If the desired pixel clock frequency is close to the limits
mentioned above, then experimentation may be used to
determine the need for the MC44145.
Frequency Divider
The frequency of the Pixel Clock is determined by the
horizontal frequency and an external frequency divider. The
divider simply divides down the Pixel Clock Frequency so
that it equals the horizontal frequency. The PLL within the
MC44011 (or the MC44145) compares the horizontal
frequency with the returned frequency, and adjusts the
internal VCO accordingly, to achieve the proper relationship
between the two. The PLL will phase–lock the
negative–going edge of the returned signal with the
positive–going edge of the Fh signal (Pin 14 of the
MC44011). The returned signal must be TTL logic level
amplitudes, and have a minimum low time of 200 ns. A
suggested circuit for the divider, shown in Figure 46, uses
74F161 programmable binary counters. The 12 switches at
the bottom are used to set the division ratio, and hence the
Pixel Clock frequency.
The division ratio is determined by dividing the desired
clock frequency by the horizontal frequency, and then using
the closest whole number. After determining the binary
equivalent of that number, close each switch corresponding
to a 1, and leave open each switch corresponding to a 0.
Alternately, the switches could be deleted, and Pins 3, 4, 5
and 6 of each 74F161 hard–wired to 5.0 V or ground, or
controlled by a microprocessor where different pixel clock
frequencies are required.
To A/D Converters
(MC44250 or MC44251)
5.0
5.0
10 k ea
1
(LSB)
5
4
8
12
(MSB)
MC44011
or
MC44145
Clock Out
Return
74F00
5.0
1.0
5.0
Gnd
CLR
VCC
RCO
QD
QC
QB
QA
A
B
C
D
LD
Clk
ENT
ENP
8
1
16
15
11
12
13
14
3
4
5
6
9
2
10
7
1.0
5.0
Gnd
CLR
VCC
RCO
QD
QC
QB
QA
A
B
C
D
LD
Clk
ENT
ENP
8
1
16
15
11
12
13
14
3
4
5
6
9
2
10
7
1.0
5.0
Gnd
CLR
VCC
RCO
QD
QC
QB
QA
A
B
C
D
LD
Clk
ENT
ENP
8
1
16
15
11
12
13
14
3
4
5
6
9
2
10
7
Figure 46. Suggested Frequency Divider
9
7
7
7
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