參數(shù)資料
型號(hào)： MC44011FN
廠商： MOTOROLA INC
元件分類： 消費(fèi)家電
英文描述： BUS CONTROLLED MULTISTANDARD VIDEO PROCESSOR
中文描述： SPECIALTY CONSUMER CIRCUIT, PQCC44
封裝： PLASTIC, LCC-44
文件頁數(shù)： 26/52頁
文件大?。?/td> 835K
代理商： MC44011FN
MC44011
26
MOTOROLA ANALOG IC DEVICE DATA
Inputs
The inputs at Pins 1 and 3 are high impedance inputs
designed to accept standard 1.0 Vpp positive video signals
(with negative going sync). The inputs are to be
capacitor–coupled so as not to upset the internal dc bias.
When normal composite video is applied, the desired input is
selected by Bit $88–7. Bits $77–6 and $77–7 must be set to
0 so that their switches are as shown in Figure 35. The
selected signal passes through the sound trap, and is then
separated by the chroma trap and the chroma (high
pass) filter.
When S–VHS signals (Y,C) are applied to the two inputs,
Bit $88–7 is used to direct the luma information to the sound
trap, and the chroma information to the ACC circuit
(Bit $77–6 must be set to a Logic 1). Bit $77–7 is normally
set to a Logic 1 in this mode to bypass the first luma delay
line and the chroma trap, but it can be left 0 if the additional
delay is desired.
Sound Trap
The sound trap will filter out any residual sound subcarrier
at the frequency selected by control bits T1 and T2 according
to Table 3. The accuracy of the notch frequency is directly
related to the selected crystal frequency.
Table 3. Sound Trap Frequency
Crystal
Frequency
T1
($7B–7)
T1
($7B–6)
Notch
Frequency
17 73 MHZ
17.73 MHZ
0
0
6.5 MHz
0
1
5.5 + 5.75 MHz
1
0
6.0 MHz
1
1
5.5 MHz
14 32 MHz
14.32 MHz
0
0
5.25 MHz
0
1
4.44 + 4.64 MHz
1
0
4.84 MHz
1
1
4.44 MHz
Code 01 (for T1, T2) is used to widen the band rejection
where stereo is in use. Typical rejection is 30 dB.
ACC and PAL/NTSC Decoder
The chroma filter bandpass characteristics (3.58 or
4.43 MHz) is determined by the selected crystal. The output
of the chroma filter is sent to the ACC circuit which detects
the burst signal, and provides automatic gain control once
the crystal oscillator has achieved phase lock–up to the
burst. The dc voltage at Pin 2 is
≈
1.5 to 2.0 V. This will occur
if the burst amplitude exceeds 30 mVpp, and if the correct
crystal is selected (Bit $7A–7). A 17.734472 MHz crystal is
required for PAL, and a 14.31818 MHz crystal is required for
NTSC. When Flag 23 is high, it indicates that the crystal’s
PLL has locked up, and the ACC circuit is active, providing
automatic gain control. A small amount of phase adjustment
(
≈ ±
5
°
) of the crystal PLL, for color correction, can be made
with control DAC $79–5/0. Pin 2 is the filter for the ACC loop,
and Pin 44 is the filter for the crystal oscillator PLL.
The PAL/NTSC decoder then determines if the signal is
PAL or NTSC by looking for the alternating phase
characteristic of the PAL burst. When Flag 24 is high, PAL
has been detected. Bits SSA, SSB, SSC, and SSD (Table 4)
must then be sent to the decoder to set the appropriate
decoding method.
Table 4. Color System Select
SSA
($7C–6)
SSB
($7D–6)
SSC
($7C–7)
SSD
($7A–6)
Color
System
0
0
0
0
Not Used
0
1
0
0
PAL
1
0
0
0
NTSC
1
1
0
0
Color Kill
X
X
1
0
External
Upon receiving the SSA to SSD bits, the decoder provides
the correct color difference signals, and with the Identification
circuit, provides the correct level at the System Select output
(Pin 34). This output is used by the MC44140 delay line.
The color kill setting (SSA = SSB = 1) should be used
when the ACC flag is 0, when the color system cannot be
properly determined, or when it is desired to have a
black–and–white output (the ACC circuit and flag will still
function if the input signal has a burst signal). The “External”
setting (SSC = 1) is used when an external (alternate) source
of color difference signals are applied to the MC44140 delay
line. (See Miscellaneous Applications Information for more
details.)
Color Difference Controls and Outputs
The color difference signals (R–Y, B–Y) from the
PAL/NTSC decoder are directed to the saturation, hue and
color balance controls, and then through a series of notch
filters before being output at Pins 41 and 42. Blanking and
clamping are applied to these outputs.
The saturation control DAC($87–5/0) varies the amplitude
of the two signals from 0 Vpp (DAC setting = 00), to a
maximum of
≈
1.8 Vpp (at a DAC setting of 63). The
maximum amplitude (without clipping) is
≈
1.5 Vpp, but a
nominal setting is
≈
1.3 Vpp at a DAC setting of 15.
The hue control ($88–5/0) varies the relative amplitude of
the two signals to provide a hue adjustment. The nominal
setting for this DAC is 32.
The color balance control ($78–5/0) provides a fine
adjustment of the relative amplitude of the two outputs. This
provides for a more accurate color setting, particularly when
NTSC signals are decoded. The nominal setting for this DAC
is 32, and should be adjusted before the hue control is
adjusted.
The notch filters provide filtering at the color burst
frequency, and at 2x and 8x that frequency. Additionally,
blanking and clamping (derived from the horizontal PLL) are
applied to the signals at this stage. The nominal output dc
level is
≈
2.0 to 2.5 Vdc, and the load applied to these outputs
should be >10 k
. Sync is not present on these outputs.
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