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參數(shù)資料
| 型號： | MC44011FN |
| 廠商： | MOTOROLA INC |
| 元件分類： | 消費家電 |
| 英文描述： | BUS CONTROLLED MULTISTANDARD VIDEO PROCESSOR |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁數(shù)： | 3/52頁 |
| 文件大小： | 835K |
| 代理商： | MC44011FN |
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MC44011
3
MOTOROLA ANALOG IC DEVICE DATA
ELECTRICAL CHARACTERISTICS
(The tested electrical characteristics are based on the conditions shown in Table 1 and
2.
Composite Video input signal = 1.0 Vpp, composed of: 0.7 Vpp Black–to–White; 0.3 Vpp Sync–to–Black; 0.3 Vpp Color Burst. VCC1 = VCC2
= VCC3 = 5.0 V, Iref = 32
μ
A (Pin 9), unless otherwise noted.)
Table 1. Control Bit Test Settings
Control Bit
Name
Value
Function
$77–7
S–VHS–Y
0
Composite Video input selected.
$77–6
S–VHS–C
0
Composite Video input selected.
$77–5
FSI
0
50 Hz Field Rate selected.
$77–4
L2 GATE
0
PLL #2 Gating enabled.
$77–3
BLCP
0
Clamp Pulse Gating enabled.
$77–2
L1 GATE
0
Vertical Gating enabled.
$77–1, 0
CB1, CA1
1,1
Vertical section Auto–Countdown mode
$78–7
36/68
μ
s
0
Time from beginning of Line 4 to Vertical Sync is 36
μ
s.
$78–6
CalKill
0
Horizontal Calibration Loop enabled.
$79–7, 6
HI, VI
1,1
Normal
$7A–7
Xtal
–
0 = 17.7 MHz crystal selected, 1 = 14.3 MHz crystal selected.
$7A–6
SSD
0
Normal
$7B–7, 6
T1, T2
1,1
Sound Trap Notch filter set to 5.5 MHz (with 17.7 MHz crystal).
$7C–7
SSC
0
Permits PAL and NTSC selection.
$7C–6, $7D–6
SSA, SSB
–
0, 1 = PAL decoding, 1,0 = NTSC decoding
$7D–7, $7E–7, 6
P1, P3, P2
1, 1, 1
Sets Luma Peaking at 0 dB.
$7F–7, 6, $80–6
D3, D1, D2
0, 0, 0
Set Luma Delay to minimum
$80–7
RGB EN
0
Fast Commutate input can enable RGB inputs.
$81–7
Y2 EN
0
Y2 input (Pin 29) deselected
$81–6
Y1 EN
1
Y1 luma path from PAL/NTSC decoder selected.
$82–7
YUV EN
0
RGB output mode selected
$82–6
YX EN
0
Disable luma matrix from RGB inputs.
$83–7
L2 Gain
0
Set PLL #2 Phase/Frequency detector gain high.
$83–6
L1 Gain
1
Set PLL #1 Phase Detector gain high.
$84–7
H Switch
0
Set Horizontal Phase Detector filter switch open.
$84–6
525/625
–
0 = 625 lines (PAL), 1 = 525 lines (NTSC)
$85–7
Fosc
÷
2
CSync
Vin Sync
H EN
0
Select direct VCO output from PLL #2.
$85–6
0
16 Fh output selected at Pin 13.
$86–7
1
Composite Video inputs (Pin 1 or 3) Sync Source selected.
$86–6
0
Enabled Horizontal Timebase.
$87–7
Y2 Sync
0
Y2 sync source not selected.
$88–7
V2/V1
1
Select Video 1 input (Pin 1).
$88–6
RGB Sync
0
RGB inputs Sync Source not selected.
Table 2. DAC Test Settings
DAC
Value
Function
DAC
Value
Function
$78
32
R–Y/B–Y Gain
$82
32
Red Contrast Trim
$79
32
Sub Carrier Phase
$83
32
Blue Brightness Trim
$7D
00
Blue Output DC Bias
$84
32
Main Brightness
$7E
00
Red Output DC Bias
$85
32
Red Brightness Trim
$7F
63
Pixel Clock VCO Gain
$86
32
Saturation (Color Diff.)
$80
32
Blue Contrast Trim
$87
16
Saturation (Decoder)
$81
32
Main Contrast
$88
32
Hue
NOTE:
Currents out of a pin are designated –, and those into a pin are designated +.
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