參數(shù)資料
型號(hào)： MC44011FN
廠商： MOTOROLA INC
元件分類： 消費(fèi)家電
英文描述： BUS CONTROLLED MULTISTANDARD VIDEO PROCESSOR
中文描述： SPECIALTY CONSUMER CIRCUIT, PQCC44
封裝： PLASTIC, LCC-44
文件頁(yè)數(shù)： 35/52頁(yè)
文件大?。?/td> 835K
代理商： MC44011FN
MC44011
35
MOTOROLA ANALOG IC DEVICE DATA
Table 14. Control Bit Description
(continued)
Control Bit
Description
Name
$84–6
525/625
This bit sets the division ratio from the crystal for the reference frequency for the Horizontal
Calibration Loop. For NTSC systems, set to 1. For PAL systems, set to 0.
$85–6
C Sync
When 0, Pin 13 will provide a square wave of
≈
250 kHz (16 x Fh). When 1, Pin 13 provides a
negative composite sync signal. See Figures 25, 27, 30, 31.
$86–7
Vin Sync
When 1, Composite Sync at the selected Video input (Pin 1 or 3) is used for all internal timing.
When 0, the Sync source is selected by Bits $87–7 and $88–6. See Table 12.
$86–6
PLL1 Enable
After power up, this bit must be set to 0, and then register $00 set to $00, to enable the Horizontal
Loop (PLL1). Setting this bit to a 1 will disable the Horizontal Loop, and engages the Calibration
Loop.
$87–7
Y2 Sync
When 1, and $86–7 = $88–6 = 0, Composite Sync at the Y2 input (Pin 29) is used for all internal
timing. When 0, the Sync source is selected by Bits $86–7 or $88–6. See Table 12.
$87–6
0
This bit must always be set to 0.
$88–7
V2/V1
When Composite Video is applied, and this bit is 0, the Video 2 input (Pin 3) is directed to the
Sound Trap. When 1, the Video 1 input (Pin 1) is selected. In S–VHS applications, when 0, Pin 3
is the Y (luma) input, and Pin 1 is the chroma input. When this bit is 1, Pin 1 is the luma input, and
Pin 3 is the chroma input.
$88–6
RGB Sync
When 1, and $86–7 = $87–7 = 0, Composite Sync at any or all of the RGB inputs (Pin 26 to 28) is
used for all internal timing. When 0, the sync source is selected by Bits $86–7 or $87–7.
See Table 12.
Table 15. Control DAC Description
Control Bits
Description
$78–5/0
This DAC allows for a relative gain adjustment of the R–Y and B–Y outputs (Pins 41, 42) as a means of adjusting the
color decoding accuracy. Nominal setting is 32.
$79–5/0
Used to balance out reference errors of the color subcarrier, primarily for NTSC. Nominal setting is 32.
Adjustment range is
≈ ±
5
°
.
$7D–5/0
Used to set the U (Pin 22) dc bias level. When in the YUV mode ($82–7 = 1), this setting should nominally be 32.
When in RGB mode, set to 00.
$7E–5/0
Used to set the V (Pin 22) dc bias level. When in the YUV mode ($82–7 = 1), this setting should nominally be 32.
When in RGB mode, set to 00.
$7F–5/0
Used to fine tune the gain of the Pixel Clock VCO to obtain optimum performance without instabilities. A setting of 63
will shut off the VCO. Setting 50 to 62 provide non–square wave outputs, and can be unstable. As the setting is
increased from 00 to 49, the gain is increased. Changing this register does not change the Pixel Clock frequency.
$80–5/0
Used to fine tune the contrast of the Blue output when in RGB mode. In YUV mode this provides a fine tuning of the
color, similar to, but not to be confused with, hue.
$81–5/0
Used to adjust the gain of the three outputs. In RGB mode this is the Contrast control.
$82–5/0
Used to fine tune the contrast of the Red output when in RGB mode. In YUV mode this provides a fine tuning of the
color, similar to, but not to be confused with, hue.
$83–5/0
Used to fine tune the brightness of the Blue output when in RGB mode. In YUV mode this provides a fine tuning of the
color, similar to, but not to be confused with, hue.
$84–5/0
Used to adjust the brightness of the three RGB outputs. In YUV mode this DAC affects only Y output (Pin 21).
$85–5/0
Used to fine tune the brightness of the Red output when in RGB mode. In YUV mode this provides a fine tuning of the
color, similar to, but not to be confused with, hue.
$86–5/0
Used to adjust the saturation of the RGB/YUV outputs of the Color Difference section.
$87–5/0
Used to adjust the saturation of the R–Y, B–Y outputs (Pins 41, 42) of the Decoder section.
$88–5/0
Used to adjust the hue of the R–Y, B–Y outputs (Pins 41, 42). Nominal setting is 32.
$00–7/0
This register must be set to 00, after Bit $86–6 is set to 0, to enable the Horizontal Loop (PLL1) after power up, or
anytime when Bit $86–6 is set to 0 after having been a 1.
NOTE:
The above DACs are 6–bits wide. The settings mentioned above, and in subsequent paragraphs are given in decimal values of 00 to 63. These are not
hex values.
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