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| 型號： | MC16S2CPU20B1 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, 20.97 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | TQFP-100 |
| 文件頁數(shù)： | 71/104頁 |
| 文件大?。?/td> | 812K |
| 代理商： | MC16S2CPU20B1 |
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MC68HC16S2
MOTOROLA
MC68HC16S2TS/D
69
4.7.2 Exception Stack Frame
During exception processing, the contents of the program counter and condition code register are
stacked at a location pointed to by SK:SP. Unless it is altered during exception processing, the stacked
PK : PC value is the address of the next instruction in the current instruction stream, plus $0006. Figure
13 shows the exception stack frame.
Figure 13 Exception Stack Frame Format
4.7.3 Exception Processing Sequence
Exception processing is performed in four phases.
1.
Priority of all pending exceptions is evaluated, and the highest priority exception is processed
first.
2.
Processor state is stacked, then the CCR PK extension field is cleared.
3.
An exception vector number is acquired and converted to a vector address.
4.
The content of the vector address is loaded into the PC, and the processor jumps to the excep-
tion handler routine.
There are variations within each phase for differing types of exceptions. However, all vectors but the
reset vectors contain 16-bit addresses, and the PK field is cleared. Exception handlers must be located
within bank 0 or vectors must point to a jump table.
4.7.4 Types of Exceptions
Exceptions can be either internally or externally generated. External exceptions, which are defined as
asynchronous, include interrupts, bus errors (BERR), breakpoints (BKPT), and resets (RESET). Inter-
nal exceptions, which are defined as synchronous, include the software interrupt (SWI) instruction, the
background (BGND) instruction, illegal instruction exceptions, and the divide-by-zero exception.
4.7.4.1 Asynchronous Exceptions
Asynchronous exceptions occur without reference to CPU16 or IMB clocks, but exception processing
is synchronized. For all asynchronous exceptions but RESET, exception processing begins at the first
instruction boundary following recognition of an exception.
Because of pipelining, the stacked return PK : PC value for all asynchronous exceptions, other than re-
set, is equal to the address of the next instruction in the current instruction stream plus $0006. The RTI
instruction, which must terminate all exception handler routines, subtracts $0006 from the stacked value
to resume execution of the interrupted instruction stream.
4.7.4.2 Synchronous Exceptions
Synchronous exception processing is part of an instruction definition. Exception processing for synchro-
nous exceptions is always completed, and the first instruction of the handler routine is always executed,
before interrupts are detected.
EX STACK FRAME
CONDITION CODE REGISTER
PROGRAM COUNTER
HIGH ADDRESS
SP AFTER EXCEPTION STACKING
SP BEFORE EXCEPTION STACKING
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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