參數(shù)資料
型號(hào)： MC16S2CPU20B1
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 16-BIT, 20.97 MHz, MICROCONTROLLER, PQFP100
封裝： TQFP-100
文件頁(yè)數(shù)： 61/104頁(yè)
文件大?。?/td> 812K
代理商： MC16S2CPU20B1
MOTOROLA
MC68HC16S2
6
MC68HC16S2TS/D
1.4 Address Map
Figure 3 is a map of the MCU internal addresses. Although there are 24 intermodule bus (IMB) address
lines, the CPU16 uses only ADDR[19:0]. ADDR[23:20] follow the logic state of ADDR19. Addresses
$080000 to $F7FFFF are not accessible. The RAM array is positioned by the base address register in
the associated RAM control block. Unimplemented blocks are mapped externally.
Figure 3 MC68HC16S2 Address Map
1.5 Intermodule Bus
The intermodule bus (IMB) is a standardized bus developed to facilitate both design and operation of
modular microcontrollers. It contains circuitry to support exception processing, address space partition-
ing, multiple interrupt levels, and vectored interrupts. The standardized modules in the MC68HC16S2
communicate with one another and with external components through the IMB. Although the full IMB
supports 24 address and 16 data lines, the MC68HC16S2 uses only 16 data lines and 20 address lines.
Because the CPU16 uses only 20 address lines, ADDR[23:20] follow the state of ADDR19.
$YFFA00
$YFFA7F
$YFFB00
$YFFB07
$000000
$FFFFFF
BASE
ADDRESS
SRAM ARRAY
2048 BYTES
SIM
128 BYTES
SRAM CTL
16S2 ADDRESS MAP
8 BYTES
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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