參數(shù)資料
型號(hào)： MC16S2CPU20B1
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 16-BIT, 20.97 MHz, MICROCONTROLLER, PQFP100
封裝： TQFP-100
文件頁(yè)數(shù)： 19/104頁(yè)
文件大?。?/td> 812K
代理商： MC16S2CPU20B1
MC68HC16S2
MOTOROLA
MC68HC16S2TS/D
21
SWT[1:0] — Software Watchdog Timing
This field selects the divide ratio used to establish software watchdog time-out period. Table 9 gives the
ratio for each combination of SWP and SWT bits.
HME — Halt Monitor Enable
0 = Disable halt monitor function
1 = Enable halt monitor function
BME — Bus Monitor Enable
0 = Disable bus monitor function for internal to external bus cycles.
1 = Enable bus monitor function for internal to external bus cycles.
BMT[1:0] — Bus Monitor Timing
This bit field selects the time-out period in system clocks for the bus monitor. Refer to Table 10.
3.4.2 Bus Monitor
The internal bus monitor checks for excessively long DSACK response times during normal bus cycles
and for excessively long DSACK or AVEC response times during interrupt acknowledge (IACK) cycles.
The monitor asserts BERR if the response time exceeds a user-specified timeout period.
DSACK and AVEC response times are measured in clock cycles. The maximum allowable response
time can be selected by setting the BMT[1:0] field.
The monitor does not check DSACK response on the external bus unless the CPU initiates the bus cy-
cle. The BME bit in SYPCR enables the internal bus monitor for internal to external bus cycles. If a sys-
tem contains external bus masters, an external bus monitor must be implemented and the internal to
external bus monitor option must be disabled.
Table 9 Software Watchdog Timing Field
SWP
SWT[1:0]
Ratio
000
29
001
211
010
213
011
215
100
218
101
220
110
222
111
224
Table 10 Bus Monitor Time-Out Period
BMT[1:0]
Bus Monitor Time-Out Period
00
64 System clocks
01
32 System clocks
10
16 System clocks
11
8 System clocks
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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