參數資料
型號： MC16S2CPU20B1
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 16-BIT, 20.97 MHz, MICROCONTROLLER, PQFP100
封裝： TQFP-100
文件頁數： 40/104頁
文件大?。?/td> 812K
代理商： MC16S2CPU20B1
MOTOROLA
MC68HC16S2
40
MC68HC16S2TS/D
Data lines have weak internal pull-up drivers. External bus loading can overcome the weak internal pull-
up drivers on data bus lines, and hold pins low during reset. Use an active device to hold data bus lines
low. Data bus configuration logic must release the bus before the first bus cycle after reset to prevent
conflict with external memory devices. The first bus cycle occurs ten CLKOUT cycles after RESET is
released. If external mode selection logic causes a conflict of this type, an isolation resistor on the driven
lines may be required.
3.8.2 Functions of Pins for Other Modules During Reset
Generally, pins associated with modules other than the SIM default to port functions, and input/output
ports are set to input state. This is accomplished by disabling pin functions in the appropriate control
registers, and by clearing the appropriate port data direction registers. Refer to individual module sec-
tions in this manual for more information. Table 32 is a summary of module pin function out of reset.
3.8.3 Reset Timing
The RESET input must be asserted for a specified minimum period in order for reset to occur. External
RESET assertion can be delayed internally for a period equal to the longest bus cycle time (or the bus
monitor timeout period) in order to protect write cycles from being aborted by reset. While RESET is
asserted, SIM pins are either in a disabled high-impedance state or are driven to their inactive states.
Table 31 Reset Mode Selection
Mode Select Pin
Default Function
(Pin Left High)
Alternate Function
(Pin Pulled Low)
DATA0
CSBOOT 16-Bit
CSBOOT 8-Bit
DATA1
CS0
CS1
CS2
BR
BG
BGACK
DATA2
CS3
CS4
CS5
FC0
FC1
FC2
DATA3
DATA4
DATA5
DATA6
DATA7
CS6
CS[7:6]
CS[8:6]
CS[9:6]
CS[10:6]
ADDR19
ADDR[20:19]
ADDR[21:19]
ADDR[22:19]
ADDR[23:19]
DATA8
DSACK[1:0]
AVEC, DS, AS
SIZ[1:0]
PORTE
DATA9
IRQ[7:1]
MODCLK
PORTF
DATA11
Test mode disabled
Test mode enabled
MODCLK
VCO = System clock
EXTAL = System clock
BKPT
Background mode disabled
Background mode enabled
Table 32 Module Pin Functions
Module
Pin Mnemonic
Function
CPU16
DSI/IPIPE1
DSO/IPIPE0
BKPT/DSCLK
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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