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| 型號： | MC16S2CPU20B1 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, 20.97 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | TQFP-100 |
| 文件頁數(shù)： | 36/104頁 |
| 文件大小： | 812K |
| 代理商： | MC16S2CPU20B1 |
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MC68HC16S2
MOTOROLA
MC68HC16S2TS/D
37
3.7 General-Purpose Input/Output
SIM pins can be configured as two general-purpose I/O ports, E and F. The following paragraphs de-
scribe registers that control the ports.
A write to the port E data register is stored in the internal data latch and, if any port E pin is configured
as an output, the value stored for that bit is driven on the pin. A read of the port E data register returns
the value at the pin only if the pin is configured as a discrete input. Otherwise, the value read is the value
stored in the register.
The port E data register is a single register that can be accessed in two locations. When accessed at
$YFFA11, the register is referred to as PORTE0; when accessed at $YFFA13, the register is referred
to as PORTE1. The register can be read or written at any time. It is unaffected by reset.
The bits in this register control the direction of the pin drivers when the pins are configured as I/O. Any
bit in this register set to one configures the corresponding pin as an output. Any bit in this register
cleared to zero configures the corresponding pin as an input. This register can be read or written at any
time.
The bits in this register control the function of each port E pin. Any bit set to one configures the corre-
sponding pin as a bus control signal, with the function shown in Table 29. Any bit cleared to zero defines
the corresponding pin to be an I/O pin, controlled by PORTE and DDRE.
Data bus bit 8 controls the state of this register following reset. If DATA8 is set to one during reset, the
register is set to $FF, which defines all port E pins as bus control signals. If DATA8 is cleared to zero
during reset, this register is set to $00, configuring all port E pins as I/O pins.
PORTC — Port C Data Register
$YFFA41
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
NOT USED
0
PC6
PC5
PC4
PC3
PC2
PC1
PC0
RESET:
0
1
PORTE0, PORTE1 — Port E Data Register
$YFFA11, YFFA13
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
NOT USED
PE7
PE6
PE5
PE4
PE3
PE2
PE1
PE0
RESET:
U
DDRE — Port E Data Direction Register
$YFFA15
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DDE7
DDE6
DDE5
DDE4
DDE3
DDE2
DDE1
DDE0
RESET:
0
PEPAR — Port E Pin Assignment
$YFFA17
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PEPA7
PEPA6
PEPA5
PEPA4
PEPA3
PEPA2
PEPA1
PEPA0
RESET:
DATA8
F
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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