- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄69028 > MC16S2CPU20B1 (FREESCALE SEMICONDUCTOR INC) 16-BIT, 20.97 MHz, MICROCONTROLLER, PQFP100 PDF資料下載
參數(shù)資料
| 型號： | MC16S2CPU20B1 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, 20.97 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | TQFP-100 |
| 文件頁數(shù)： | 12/104頁 |
| 文件大?。?/td> | 812K |
| 代理商： | MC16S2CPU20B1 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁當(dāng)前第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁
MC68HC16S2
MOTOROLA
MC68HC16S2TS/D
15
Figure 6 System Clock Oscillator Circuit
When an external system clock signal is applied (PLL disabled, MODCLK = 0 during reset), the duty
cycle of the input is critical, especially at operating frequencies close to maximum. The relationship be-
tween clock signal duty cycle and clock signal period is expressed:
When the system clock signal is applied directly to the EXTAL pin (PLL is disabled, MODCLK = 0 during
reset), or the clock synthesizer reference frequency is supplied by a source other than a crystal (PLL
enabled, MODCLK = 1 during reset), the XTAL pin must be left floating. In either case, the frequency of
the signal applied to EXTAL may not exceed the maximum system clock frequency (PLL disabled) or
the maximum clock synthesizer reference frequency (PLL enabled).
3.3.2 Clock Synthesizer Operation
VDDSYN is used to power the clock circuits when the phase-locked loop is used. A separate power
source increases MCU noise immunity and can be used to run the clock when the MCU is powered
down. A quiet power supply must be used as the VDDSYN source. Adequate external bypass capacitors
should be placed as close as possible to the VDDSYN pin to assure stable operating frequency. When
an external system clock signal is applied and the PLL is disabled, VDDSYN should be connected to the
VDD supply. Refer to the SIM Reference Manual (SIMRM/AD) for more information regarding system
clock power supply conditioning.
A voltage controlled oscillator (VCO) generates the system clock signal. To maintain a 50% clock duty
cycle, the VCO frequency (fVCO) is either two or four times the system clock frequency, depending on
the state of the X bit in SYNCR. A portion of the clock signal is fed back to a divider/counter. The divider
controls the frequency of one input to a phase comparator. The other phase comparator input is the
reference signal connected to the EXTAL pin. The comparator generates a control signal proportional
to the difference in phase between the two inputs. The signal is low-pass filtered and used to correct
the VCO output frequency.
Filter circuit implementation can vary, depending upon the external environment and required clock sta-
bility. Figure 7 shows a recommended system clock filter network. XFC pin leakage must be kept within
specified limits to maintain optimum stability and PLL performance.
An external filter network connected to the XFC pin is not required when an external system clock signal
is applied and the PLL is disabled. The XFC pin must be left floating in this case.
32 OSCILLATOR
EXTAL
XTAL
10 M
330 k
22 pF*
VSSI
RESISTANCE AND CAPACITANCE BASED ON A TEST CIRCUIT CONSTRUCTED WITH A DAISHINKU DMX-38 32.768 kHz CRYSTAL.
SPECIFIC COMPONENTS MUST BE BASED ON CRYSTAL TYPE. CONTACT CRYSTAL VENDOR FOR EXACT CIRCUIT.
*
R1
C1
C2
R2
Minimum External Clock Period
Minimum External Clock High/Low Time
50 %
Percentage Variation of External Clock Input Duty Cycle
–
------------------------------------------------------------------------------------------------------------------------------------------------------------------------
=
F
re
e
sc
a
le
S
e
m
ic
o
n
d
u
c
to
r,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
c
..
.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MC68HC16X1CTH | 16-BIT, MROM, 16.78 MHz, MICROCONTROLLER, PQFP120 |
| MC68HC24VP | 16 I/O, PIA-GENERAL PURPOSE, PDIP40 |
| MC68HC33CFG | 48 I/O, PIA-GENERAL PURPOSE, PQFP100 |
| MC68HC33FG | 48 I/O, PIA-GENERAL PURPOSE, PQFP100 |
| MC68HC56FN | 1 CHANNEL(S), LOCAL AREA NETWORK CONTROLLER, PQCC28 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC16XSD200FK | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Dual 16 mOhm High Side Switch |
| MC16Z1CFC25B1 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MC16Z1CPV20B1 | 制造商:Rochester Electronics LLC 功能描述:16 BIT MCU, 1K RAM - Bulk |
| MC16Z3BCAG16 | 功能描述:16位微控制器 - MCU 16BIT MCU 4KRAM 8KROM RoHS:否 制造商:Texas Instruments 核心:RISC 處理器系列:MSP430FR572x 數(shù)據(jù)總線寬度:16 bit 最大時鐘頻率:24 MHz 程序存儲器大小:8 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:VQFN-40 安裝風(fēng)格:SMD/SMT |
| MC-17 | 功能描述:TERM BARRIER 17CIRC DUAL ROW RoHS:是 類別:連接器，互連式 >> 接線座 - 隔板塊 系列:M 標(biāo)準(zhǔn)包裝:10 系列:Beau™ 38780 端接塊類型:阻隔塊 電路數(shù):15 導(dǎo)線入口數(shù)目:30 間距:0.438"（11.12mm） 行數(shù):2 電流:15A 電壓:300V 線規(guī):14-22 AWG 頂部端子:螺釘 底部端子:焊片 阻擋層類型:雙壁（雙） 特點:法蘭 顏色:黑 包裝:散裝 安裝類型:通孔 工作溫度:- 材料 - 絕緣體:聚對苯二甲酸丁二酯（PBT），玻璃纖維增強型 材料可燃性額定值:UL94 V-0 其它名稱:038780-111538780-1115387801115 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。