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參數(shù)資料
| 型號： | MC16S2CPU20B1 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, 20.97 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | TQFP-100 |
| 文件頁數(shù)： | 14/104頁 |
| 文件大小： | 812K |
| 代理商： | MC16S2CPU20B1 |
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MC68HC16S2
MOTOROLA
MC68HC16S2TS/D
17
When the on-chip clock synthesizer is used, system clock frequency is controlled by the bits in the upper
byte of SYNCR. Bits in the lower byte show the status of or control the operation of internal and external
clocks. SYNCR can be read or written only when the CPU is operating in supervisor mode.
W — Frequency Control (VCO)
This bit controls a prescaler tap in the synthesizer feedback loop. Setting it increases the VCO speed
by a factor of four. VCO relock delay is required.
X — Frequency Control (Prescaler)
This bit controls a divide by two prescaler that is not in the synthesizer feedback loop. Setting it doubles
the clock speed without changing the VCO speed. No VCO relock delay is required.
Y[5:0] — Frequency Control (Counter)
The Y field controls the modulus down counter in the synthesizer feedback loop, causing it to divide by
a value of Y + 1. Values range from zero to 63. VCO relock delay is required.
EDIV — E Clock Divide Rate
0 = ECLK frequency is system clock divided by eight.
1 = ECLK frequency is system clock divided by 16.
ECLK is an external M6800 bus clock available on pin ADDR23. Refer to 3.6 Chip-Selects for more
information.
SLOCK — Synthesizer Lock Flag
0 = VCO has not locked, but is enabled on the desired frequency.
1 = VCO has locked on the desired frequency, or is disabled.
The MCU remains in reset until the synthesizer locks, but SLOCK does not indicate synthesizer lock
status until after the user writes to SYNCR.
STSIM — Stop Mode SIM Clock
0 = When LPSTOP is executed, the SIM clock is driven by the crystal oscillator and the VCO is
turned off to conserve power.
1 = When LPSTOP is executed, the SIM clock is driven by the VCO.
STEXT — Stop Mode External Clock
0 = When LPSTOP is executed, the CLKOUT signal is held negated to conserve power.
1 = When LPSTOP is executed, the CLKOUT signal is driven by the SIM clock, as determined by
the state of the STSIM bit.
3.3.4 External MC6800 Bus Clock
The state of the ECLK division rate bit (EDIV) in SYNCR determines clock rate for the ECLK signal avail-
able on pin ADDR23. ECLK is a bus clock for MC6800 devices and peripherals. ECLK frequency can
be set to system clock frequency divided by eight or system clock frequency divided by sixteen. The
clock is enabled by the CS10 field in chip-select pin assignment register 1 (CSPAR1). ECLK operation
during low-power stop is described in the following paragraph. Refer to 3.6 Chip-Selects for more in-
formation about the external bus clock.
3.3.5 Low-Power Operation
Low-power operation is initiated by the CPU16. To reduce power consumption selectively, the CPU16
can enter the following low-power modes:
1.
The CPU16 can selectively disable a module by setting the module’s STOP bit.
2.
The CPU16 can execute the LPSTOP instruction to stop the operations of the entire MCU.
If the STOP bit in a module is set, then that module enters a low power mode. Some or all of that mod-
ule’s registers remain accessible. The module can be restarted by asserting RESET or by the CPU16
clearing the module’s STOP bit.
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For More Information On This Product,
Go to: www.freescale.com
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