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| 型號： | MC16S2CPU20B1 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, 20.97 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | TQFP-100 |
| 文件頁數(shù)： | 23/104頁 |
| 文件大?。?/td> | 812K |
| 代理商： | MC16S2CPU20B1 |
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MC68HC16S2
MOTOROLA
MC68HC16S2TS/D
25
3.5.2 Function Codes
Function code signals FC[2:0] are automatically generated by the CPU16. The function codes can be
considered address extensions that automatically select one of eight address spaces to which an ad-
dress applies. These spaces are designated as either user or supervisor, and program or data spaces.
Because the CPU16 always operates in supervisor mode (FC2 always = 1), address spaces 0 to 3 are
not used. Address space 7 is designated CPU space. CPU space is used for control information not
normally associated with read or write bus cycles. Function codes are valid while AS is asserted.
Table 14 displays CPU16 address space encodings.
3.5.3 Address Bus
Address bus signals ADDR[19:0] define the address of the most significant byte to be transferred during
a bus cycle. The MCU places the address on the bus at the beginning of a bus cycle. The address is
valid while AS is asserted. Because the CPU16 in the MC68HC16S2 does not drive ADDR[23:20],
these lines follow the logic state of ADDR19.
3.5.4 Address Strobe
AS is a timing signal that indicates the validity of an address on the address bus and the validity of many
control signals. It is asserted one-half clock after the beginning of a bus cycle.
3.5.5 Data Bus
Data bus signals DATA[15:0] make up a bidirectional, non-multiplexed parallel bus that transfers data
to or from the MCU. A read or write operation can transfer eight or 16 bits of data in one bus cycle. Dur-
ing a read cycle, the data is latched by the MCU on the last falling edge of the clock for that bus cycle.
For a write cycle, all 16 bits of the data bus are driven, regardless of the port width or operand size. The
MCU places the data on the data bus one-half clock cycle after AS is asserted in a write cycle.
3.5.6 Data Strobe
Data strobe (DS) is a timing signal. For a read cycle, the MCU asserts DS to signal an external device
to place data on the bus. DS is asserted at the same time as AS during a read cycle. For a write cycle,
DS signals an external device that data on the bus is valid. The MCU asserts DS one full clock cycle
after the assertion of AS during a write cycle.
3.5.7 Bus Cycle Termination Signals
During bus cycles, external devices assert the data size acknowledge signals DSACK1 and DSACK0.
During a read cycle, the signals tell the MCU to terminate the bus cycle and to latch data. During a write
cycle, the signals indicate that an external device has successfully stored data and that the cycle can
end. These signals also indicate to the MCU the size of the port for the bus cycle just completed. Alter-
nately, chip-selects can be used to generate DSACK1 and DSACK0 internally. Refer to 3.5.8 Dynamic
Bus Sizing for more information.
Table 14 CPU16 Address Space Encoding
FC2
FC1
FC0
Address Space
1
0
Reserved
1
0
1
Data space
1
0
Program space
1
CPU space
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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