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參數(shù)資料
| 型號： | MC13214R2 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, BGA71 |
| 封裝： | 9 X 9 MM, 1 MM HEIGHT, ROHS COMPLIANT, LGA-71 |
| 文件頁數(shù)： | 7/70頁 |
| 文件大小： | 802K |
| 代理商： | MC13214R2 |
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MC13211/212/213/214 Technical Data, Rev. 0.0,
Freescale Semiconductor
15
3.2
SPI Features
MCU bus master
Modem bus slave
Programmable SPI clock rate; maximum rate is 8 MHz
Double-buffered transmit and receive at MCU
Serial clock phase and polarity must meet modem requirements (MCU control bits
Slave select programmed to meet modem protocol
3.3
SPI System Block Diagram
Figure 5 shows the SPI system level diagram.
Figure 5. SPI System Block Diagram
Figure 5 shows the SPI modules of the MCU and modem in the master-slave arrangement. The MCU
(master) initiates all SPI transfers. During a transfer, the master shifts data out (on the MOSI pin) to the
slave while simultaneously shifting data in (on the MISO pin) from the slave. Although the SPI interface
supports simultaneous data exchange between master and slave, the modem SPI protocol only uses data
exchange in one direction at a time. The SPSCK signal is a clock output from the master and an input to
the slave. The slave device must be selected by a low level on the slave select input (SS1 pin).
7
6
5
4
3
2
1
0
SPI SHIFTER
CLOCK
GENERATOR
7
6
5
4
3
2
1
0
SPI SHIFTER
PTE2/SS1
SPSCK1
MISO1
MOS1
CE
SPICLK
MISO
MOSI
MCU (MASTER)
MODEM (SLAVE)
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