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參數(shù)資料
| 型號： | MC13214R2 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, BGA71 |
| 封裝： | 9 X 9 MM, 1 MM HEIGHT, ROHS COMPLIANT, LGA-71 |
| 文件頁數(shù)： | 13/70頁 |
| 文件大?。?/td> | 802K |
| 代理商： | MC13214R2 |
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MC13211/212/213/214 Technical Data, Rev. 0.0,
20
Freescale Semiconductor
NOTE
For the MCU, the SPI clock format is the clock phase control bit CPHA = 0
and the clock polarity control bit CPOL = 0.
3. Master Out/Slave In (MOSI) - Incoming data from the host is presented on the MOSI input.
4. Master In/Slave Out (MISO) - The 802.15.4 modem presents data to the master on the MISO
output.
Although the SPI port is fully static, internal memory, timer and interrupt arbiters require an internal clock
(CLKcore), derived from the crystal reference oscillator, to communicate from the SPI registers to internal
registers and memory.
4.6.2.1
SPI Burst Operation
The SPI port of the MCU transfers data in bursts of 8 bits with most significant bit (MSB) first. The master
(MCU) can send a byte to the slave (transceiver) on the MOSI line and the slave can send a byte to the
master on the MISO line. Although an 802.15.4 modem transaction is three or more SPI bursts long, the
timing of a single SPI burst is shown in Figure 10. The maximum SPI clock rate is 8 Mhz from the MCU
because the modem is limited by this number.
Figure 10. SPI Single Burst Timing Diagram
1
23
4
5
6
7
8
CE
SPICLK
SPI Burst
Valid
MISO
MOSI
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| MC1321X | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述: |
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| MC13224V | 制造商:Freescale Semiconductor 功能描述:; Controller Family/Series:(ARM7); Memor |
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