參數(shù)資料
型號(hào): MC13214R2
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: SPECIALTY MICROPROCESSOR CIRCUIT, BGA71
封裝: 9 X 9 MM, 1 MM HEIGHT, ROHS COMPLIANT, LGA-71
文件頁數(shù): 55/70頁
文件大小: 802K
代理商: MC13214R2
MC13211/212/213/214 Technical Data, Rev. 0.0,
Freescale Semiconductor
59
Figure 28. Control Reset Timing
Figure 29. Control Active Background Debug Mode Latch Timing
Figure 30. Control IRQ Timing
6.4.2
MCU Timer/PWM (TPM) Module Timing
Synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that
can be used as the optional external source to the timer counter. These synchronizers operate from the
current bus rate clock.
1 This is the shortest pulse that is guaranteed to be recognized as a reset pin request. Shorter pulses are not guaranteed to
override reset requests from internal sources.
2 When any reset is initiated, internal circuitry drives the reset pin low for about 34 cycles of f
Self_reset and then samples the
level on the reset pin about 38 cycles later to distinguish external reset requests from internal requests.
3 This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or
may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized in that case.
4 Timing is shown with respect to 20% V
DD and 80% VDD levels. Temperature range –40°C to 85°C.
Table 18. TPM Input Timing
Function
Symbol
Min
Max
Unit
External clock frequency
fTPMext
dc
fBus/4
MHz
External clock period
tTPMext
4—
tcyc
External clock high time
tclkh
1.5
tcyc
External clock low time
tclkl
1.5
tcyc
Input capture pulse width
tICPW
1.5
tcyc
textrst
RESET PIN
BKGD/MS
RESET
tMSSU
tMSH
tILIH
IRQ
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