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參數(shù)資料
| 型號(hào)： | MC13214R2 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, BGA71 |
| 封裝： | 9 X 9 MM, 1 MM HEIGHT, ROHS COMPLIANT, LGA-71 |
| 文件頁(yè)數(shù)： | 28/70頁(yè) |
| 文件大?。?/td> | 802K |
| 代理商： | MC13214R2 |
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MC13211/212/213/214 Technical Data, Rev. 0.0,
34
Freescale Semiconductor
5.7.1.1
SPI Features
Features of the SPI module use include:
Used in master mode only
Programmable transmit bit rate (maximum usable rate is 8 MHz with modem)
Double-buffered transmit and receive
Serial clock phase and polarity option must be programmed to CPHA = 0 and CPOL = 0
Programmable slave select output to support modem SPI protocol
MSB-first data transfer
5.7.1.2
SPI Module Block Diagram
Figure 19 is a block diagram of the SPI module. The central element of the SPI is the SPI shift register.
Data is written to the double-buffered transmitter (write to SPI1D) and gets transferred to the SPI shift
register at the start of a data transfer. After shifting in a byte of data, the data is transferred into the
double-buffered receiver where it can be read (read from SPI1D). Pin multiplexing logic controls
connections between MCU pins and the SPI module.
When the SPI is configured as a master, the clock output is routed to the SPSCK pin, the shifter output is
routed to MOSI, and the shifter input is routed from the MISO pin.
Figure 19. Modem Dedicated SPI Block Diagram
SPI SHIFT REGISTER
SHIFT
CLOCK
SHIFT
DIRECTION
Rx BUFFER
FULL
Tx BUFFER
EMPTY
SHIFT
OUT
SHIFT
IN
ENABLE
SPI SYSTEM
CLOCK
LOGIC
CLOCK GENERATOR
BUS RATE
CLOCK
MASTER/SLAVE
MODE SELECT
MODE FAULT
DETECTION
MASTER CLOCK
SLAVE CLOCK
SPI
INTERRUPT
REQUEST
PIN CONTROL
M
S
MASTER/
SLAVE
MOSI
MISO
SPSCK
SS
M
S
M
MODF
SPE
LSBFE
MSTR
SPRF
SPTEF
SPTIE
SPIE
MOD-
SSOE
SPC0
BIDIROE
SPIBR
Tx BUFFER (WRITE
Rx BUFFER (READ)
MOSI
MISO
SPICLK
CE
MODEM
SPI
PORT
Connected onboard SiP
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