參數(shù)資料
型號： MC13214R2
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： SPECIALTY MICROPROCESSOR CIRCUIT, BGA71
封裝： 9 X 9 MM, 1 MM HEIGHT, ROHS COMPLIANT, LGA-71
文件頁數(shù)： 54/70頁
文件大?。?/td> 802K
代理商： MC13214R2
MC13211/212/213/214 Technical Data, Rev. 0.0,
58
Freescale Semiconductor
6.4
MCU AC Peripheral Characteristics
This section describes ac timing characteristics for each peripheral system.
6.4.1
MCU Control Timing
ICGOUT period jitter, 4, 7 measured at fICGOUT Max
Long term jitter (averaged over 2 ms interval)
CJitter
—0.2
% fICG
Internal oscillator deviation from trimmed frequency
VDD = 1.8 – 3.6 V, (constant temperature)
VDD = 3.0 V ±10%, –40° C to 85° C
ACCint
—
±0.5
±2
%
1 Self-clocked mode frequency is the frequency that the DCO generates when the FLL is open-loop.
2 Loss of reference frequency is the reference frequency detected internally, which transitions the ICG into self-clocked mode if
it is not in the desired range.
3 Loss of DCO frequency is the DCO frequency detected internally, which transitions the ICG into FLL bypassed external mode
(if an external reference exists) if it is not in the desired range.
4 This parameter is characterized before qualification rather than 100% tested.
5 Proper PC board layout procedures must be followed to achieve specifications.
6 This specification applies to the period of time required for the FLL to lock after entering FLL engaged internal or external
modes. If a crystal/resonator is being used as the reference, this specification assumes it is already running.
7 Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f
ICGOUT.
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise
injected into the FLL circuitry via VDDA and VSSA and variation in crystal oscillator frequency increase the CJitter percentage
for a given interval.
Table 17. MCU Control Timing
Parameter
Symbol
Min
Typical
Max
Unit
Bus frequency (tcyc = 1/fBus)fBus
dc
—
20
MHz
Real-time interrupt internal oscillator period
tRTI
700
1300
s
External reset pulse width1
textrst
1.5 x
fSelf_reset
—ns
Reset low drive2
trstdrv
34 x
fSelf_reset
—ns
Active background debug mode latch setup time
tMSSU
25
—
ns
Active background debug mode latch hold time
tMSH
25
—
ns
IRQ pulse width3
tILIH
1.5 x tcyc
—ns
Port rise and fall time (load = 50 pF)4
Slew rate control disabled
Slew rate control enabled
tRise, tFall
—
3
30
ns
Table 16. MCU ICG Frequency Specifications (continued)
(VDDA = VDDA (min) to VDDA (max), Temperature Range = –40 to 85°C Ambient)
Characteristic
Symbol
Min
Typical
Max
Unit
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