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參數(shù)資料
| 型號(hào)： | MC13214R2 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, BGA71 |
| 封裝： | 9 X 9 MM, 1 MM HEIGHT, ROHS COMPLIANT, LGA-71 |
| 文件頁數(shù)： | 20/70頁 |
| 文件大小： | 802K |
| 代理商： | MC13214R2 |
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MC13211/212/213/214 Technical Data, Rev. 0.0,
Freescale Semiconductor
27
When the MCU is in Stop2 Mode, all internal circuits that are powered from the voltage regulator are
turned off, except for the RAM. The voltage regulator is in a low-power standby state, as is the ATD. Upon
entry into Stop2, the states of the I/O pins are latched. The states are held while in Stop2 Mode and after
exiting Stop2 Mode until a 1 is written to PPDACK in SPMSC2.
Exit from Stop2 is performed by asserting either of the wake-up pins: RESET or IRQ, or by an RTI
interrupt. IRQ is always an active low input when the MCU is in Stop2, regardless of how it was
configured before entering Stop2.
Upon wake-up from Stop2 Mode, the MCU will start up as from a power-on reset (POR) except pin states
remain latched. The CPU will take the reset vector. The system and all peripherals will be in their default
reset states and must be initialized.
After waking up from Stop2, the PPDF bit in SPMSC2 is set. This flag may be used to direct user code to
go to a Stop2 recovery routine. PPDF remains set and the I/O pin states remain latched until a 1 is written
to PPDACK in SPMSC2.
To maintain I/O state for pins that were configured as general-purpose I/O, the user must restore the
contents of the I/O port registers, which have been saved in RAM, to the port registers before writing to
the PPDACK bit. If the port registers are not restored from RAM before writing to PPDACK, then the
register bits will assume their reset states when the I/O pin latches are opened and the I/O pins will switch
to their reset states.
For pins that were configured as peripheral I/O, the user must reconfigure the peripheral module that
interfaces to the pin before writing to the PPDACK bit. If the peripheral module is not enabled before
writing to PPDACK, the pins will be controlled by their associated port control registers when the I/O
latches are opened.
A separate self-clocked source (approximately 1 kHz) for the real-time interrupt allows a walk-up from
Stop2 or Stop3 Modes with no external components. When RTIS2:RTIS1:RTIS0 = 0:0:0, the real-time
interrupt function and this 1-kHz source are disabled. Power consumption is lower when the 1-kHz source
is disabled, but in that case the real-time interrupt cannot wake the MCU from stop.
5.2.4
Stop3
Upon entering the Stop3 Mode, all of the clocks in the MCU, including the oscillator itself, are halted. The
ICG is turned off, the ATD is disabled, and the voltage regulator is put in standby. The states of all of the
internal registers and logic, as well as the RAM content, are maintained. The I/O pin states are not latched
at the pin as in Stop2. Instead they are maintained by virtue of the states of the internal logic driving the
pins being maintained.
Exit from Stop3 is performed by asserting RESET, an asynchronous interrupt pin, or through the real-time
interrupt. The asynchronous interrupt pins are the IRQ or KBI pins.
If Stop3 is exited by means of the RESET pin, then the MCU will be reset and operation will resume after
taking the reset vector. Exit by means of an asynchronous interrupt or the real-time interrupt will result in
the MCU taking the appropriate interrupt vector.
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