參數(shù)資料
型號(hào)： MC13214R2
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： SPECIALTY MICROPROCESSOR CIRCUIT, BGA71
封裝： 9 X 9 MM, 1 MM HEIGHT, ROHS COMPLIANT, LGA-71
文件頁數(shù)： 25/70頁
文件大小： 802K
代理商： MC13214R2
MC13211/212/213/214 Technical Data, Rev. 0.0,
Freescale Semiconductor
31
— FLL engaged external locked is a state which occurs when the FLL detects that the DCO is
locked to a multiple of the internal reference.
Figure 17 is a top-level diagram that shows the functional organization of the internal clock generation
(ICG) module.
Figure 17. ICG Block Diagram
5.5
Central Processing Unit (CPU)
The HCS08 CPU is fully source- and object-code-compatible with the M68HC08 CPU. Several
instructions and enhanced addressing modes were added to improve C compiler efficiency and to support
a new background debug system which replaces the monitor mode of earlier M68HC08 microcontrollers
(MCU).
5.5.1
CPU Features
Features of the CPU include:
Object code fully upward-compatible with M68HC05 and M68HC08 Families
All registers and memory are mapped to a single 64-Kbyte address space
16-bit stack pointer (any size stack anywhere in 64-Kbyte address space)
16-bit index register (H:X) with powerful indexed addressing modes
8-bit accumulator (A)
Many instructions treat X as a second general-purpose 8-bit register
Seven addressing modes:
OSCILLATOR (OSC)
FREQUENCY
INTERNAL
EXTAL
XTAL
REFERENCE
GENERATORS
CLOCK
SELECT
8 MHz
IRG
LOSS OF LOCK
AND CLOCK DETECTOR
LOCKED
LOOP (FLL)
FIXED
CLOCK
SELECT
ICGOUT
TYP 243 kHz
RG
ICGLCLK
ICG
FFE
VDD
VSS
DCO
WITH EXTERNAL REF
SELECT
REF
SELECT
LOCAL CLOCK FOR OPTIONAL USE WITH BDC
OUTPUT
CLOCK
SELECT
ICGDCLK
/R
ICGERCLK
ICGIRCLK
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