
6.3 Registers and register details
MB90580 Series
Chapter 6: Low Power Control Circuit
65
6.3.2 CKSCR (Clock selection register)
[Bit 15] SCM
This bit indicates whether the main clock or the subclock is selected as the machine clock. When this
bit is "0", it indicates that the subclock is selected; when this bit is "1", it indicates that the main clock is
selected. If SCS = 0 and SCM = 1, it indicates that the main clock oscillation stabilization waiting period
is in progress.
[Bit 14] MCM
This bit indicates whether the main clock or the PLL clock is selected as the machine clock. When this
bit is "0", it indicates that the PLL clock is selected; when this bit is "1", it indicates that the main clock is
selected. If MCS = 0 and MCM = 1, it indicates that the PLL clock oscillation stabilization waiting period
is in progress. Note that the PLL clock oscillation stabilization waiting period is fixed at 2
12
main clock
cycles.
[Bits 13, 12] WS1, WS0
These bits set the main clock oscillation stabilization waiting period upon wake-up from stop mode or
hardware standby mode is released.
These bits are initialized to "11" by a power-on reset; these bits are not initialized by a reset due to
other sources. These bits can be read and written.
Table 6.3.2a WS Bit Settings
[Bit 11] SCS
This bit selects either the main clock or the subclock as the machine clock. When a "0" is written to this
bit, the subclock is selected; when a "1" is written to this bit, the main clock is selected. If a "1" is
written to this bit while it is "0", the oscillation stabilization waiting period for the main clock is generated;
therefore, the timebase timer is automatically cleared. In addition, the subclock (as is) is used for the
operation clock when the subclock is selected. (When the source oscillation is 32 kHz, the operation
clock is 32 KHz.) When SCS and MCS are both set to "0", SCS takes priority and the subclock is
selected.
This bit is initialized to "1" by a reset due to power-on, hardware standby, the watchdog timer, an
external source, or software.
WS1
WS0
Oscillation stabilization waiting period
(source oscillation at 4 MHz)
0
0
No oscillation stabilization waiting period
0
1
Approx. 1.02 ms (count of 2
14
of the source oscillation)
1
0
Approx. 8.19 ms (count of 2
16
of the source oscillation)
1
1
Approx. 65.54 ms (count of 2
18
of the source oscillation)
MCS
CS1
SCS
WS0
WS1
MCM
Address: 0000A1
H
Read/write
Initial value
Bit No.
(R)
(1)
(R/W)
(1)
(R/W)
(1)
(R/W)
(0)
CKSCR
(R)
(1)
(R/W)
(1)
SCM
(R/W)
(1)
(R/W)
(0)
CS0
15
14
13
12
11
10
9
8
Clock selection register