
13.3 Registers and Register Details
148
Chapter 13: IE Bus
MB90580 Series
13.3.2 Command register lower byte (CMRL)
[bit 7] RXS
RX input pin polarity selected for external driver/receiver.
Table 13.3.2a Interval for the occurrence of data transmit interrupt
[bit 6] TXS
TX output pin polarity selected for external driver/receiver.
Table 13.3.2b Interval for the occurrence of data transmit interrupt
Note1:
For MB90580 series, during reset, TX pin will output ‘L’. If the driver/receiver used is
in positive logic (Driver/receiver enable at ‘L’), TX outputs ‘L’ from reset to bit setting
that will generate a communication error when there is a communication between
other communication units. When it happens, it needs a outside circuit to input ‘H’ to
the driver/receiver from reset to bit setting.
[bit 5, 4] TIT1, TIT0 (Data transmit interrupt control bits)
These bits control the time interval of the occurrence of interrupt for writing transmit data in write data
buffer (WDB).
Table 13.3.2c Interval for the occurrence of data transmit interrupt
RXS
RX input status
0
RX pin as postive logic input. Logic ‘1’ is high level and Logic ‘0’ is Low level.
1
RX pin as negative logic input. Logic ‘1’ is low level and Logic ‘0’ is high level.
TXS
TX output
0
TX pin as postive logic output. Logic ‘1’ is high level and Logic ‘0’ is Low level.
1
TX pin as negative logic output. Logic ‘1’ is low level and Logic ‘0’ is high level.
TIT1
TIT0
Timing for interrupt occurs
0
0
More than one byte data can be written in WDB
0
1
More than two byte data can be written in WDB
1
0
More than four byte data can be written in WDB
1
1
Eight byte data can be written in WDB
CS1
CS0
TIT0
TIT1
CMRL
Address: 000076
H
RXS
TXS
(R/W)
(1)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(1)
(R/W)
(0)
(R/W)
(0)
Bit Number.
7
6
5
4
3
2
1
0
RDBC
WDBC
Command register lower byte (CMRL)
Read/write
Initial value