
MB90580 Series
xvii
TABLES
Chapter 1 Overview ............................................................................................................................................1
Table 1.2a
MB90580 series product lineup ....................................................................................3
Table 1.5a
Pin functions (1/4) (STBC: With standby control) ......................................................7
Table 1.5b
Pin functions (2/4) .........................................................................................................8
Table 1.5c
Pin functions (3/4) .........................................................................................................9
Table 1.5d
Pin functions (4/4) .......................................................................................................10
Table 1.5e
I/O circuit format (1) ....................................................................................................11
Table 1.5f
I/O circuit format (2) ....................................................................................................12
Table 1.5g
I/O circuit format (3) ....................................................................................................13
Chapter 2 CPU ..................................................................................................................................................15
Table 2.1.1a
Default space ..............................................................................................................18
Table 2.1.2a
Levels indicated by the interrupt level mask (ILM) register .........................................25
Table 2.1.2b
Register functions ......................................................................................................26
Table 2.1.2c
Relationship between registers ...................................................................................26
Table 2.1.3a
Bank select prefix .......................................................................................................28
Chapter 3 Memory ............................................................................................................................................31
Table 3.1a
Memory Access Mode ................................................................................................31
Table 3.1.1a
Mode pins and modes ................................................................................................32
Table 3.1.3a
Sample recommended setting of mode pins and mode data .....................................35
Table 3.1.3b
Modes and related external pin operations .................................................................35
Table 3.2.0a
Selecting the high-order address bit output control ....................................................39
Chapter 4 Clock and Reset ..............................................................................................................................47
Table 4.2a
Reset causes ..............................................................................................................48
Table 4.2b
Reset cause bits .........................................................................................................49
Chapter 5 Watchdog Timer, Timebase Timer, and Watch Timer Functions ...............................................51
Table 5.3.1a
Reset cause registers .................................................................................................54
Table 5.3.1b
Watchdog Timer Interval Selection Bits ......................................................................55
Table 5.3.2a
Selecting the time base timer interval .........................................................................56
Table 5.3.3a
Watch Timer Interval Selection ...................................................................................58
Chapter 6 Low Power Control Circuit .............................................................................................................61
Table 6.3.1a
CG Bit Setting .............................................................................................................64
Table 6.3.2a
WS Bit Settings ...........................................................................................................65
Table 6.3.2b
CS Bit Settings ............................................................................................................66
Table 6.4a
Low Power Consumption Mode Operating Statuses ..................................................67
Table 6.4.9a
List of Transition Conditions .......................................................................................74
Chapter 7 Interrupt ...........................................................................................................................................81
Table 7.2a
Interrupt causes, interrupt vectors, and interrupt control registers .............................82