
6.2 Block Diagram
62
Chapter 6: Low Power Control Circuit
MB90580 Series
6.2 Block Diagram
Figure 6.2a Low-power consumption control circuit and clock generator
F
2
M
Subclock
(OSC oscillation)
Main clock
(OSC oscillation)
CPU clock
0/9/17/33 intermittent
cycle selection
SCM
SLEEP
Standby
MSTP
Control circuit
STOP
RST
Cancel
HST start
Peripheral clock
Main OSC stop
Sub OSC stop
Interrupt request
or RST
Pin high-impedance
control circuit
Pin HI-Z
Self-refresh
RSTX pin
Internal RST
To watchdog timer
PLL multiplier circuit
1 2 3 4
CPU clock selector
1/2 S
Subclock switching
controller
CPU system
clock
generation
CPU intermittent
operation function
cycle number
selection circuit
Peripheral
system clock
generation
Oscillation
stabilization
wait time
selector
Self-refresh control circuit
Internal reset
generation circuit
Clock input
Timebase timer
2
4
2
13
2
15
2
18
2
12
2
14
2
16
2
19
CKSCR
SCM
SCS
CKSCR
MCM
MCS
CKSCR
CS1
CS0
LPMCR
CG1
CG0
LPMCR
SLP
STP
TMD
CKSCR
WS1
WS0
SPL
SSR
RST
LPMCR
LPMCR
HSTX pin
WDGRST