
4.2 Reset Causes
48
Chapter 4: Clock and Reset
MB90580 Series
4.2 Reset Causes
When a reset cause occurs, F
2
MC-16LX terminates the currently executing processing and waits for the
release of reset signal. A reset can be caused by the following factors:
H
Power-on reset
H
Hardware standby release
H
Watch-dog timer overflow
H
External reset request via RSTX pin
H
Reset request by software
Right after stop mode release or power on reset, the MCU will wait for the stabilization time before
resumption of any activities.
When reset occurs, F
2
MC-16LX will stop all operation at once and wait for the release of reset.
The content of watchdog timer control register will change according to the reset cause. Thus, the cause of
previous reset can be known.
Note:
While an external bus is used, the address generated by the device is undefined when
a reset cause occurs. All external bus access signals, including RDX and WRX,
become inactive.
* In stop or hardware standby mode, a reset input allows for oscillation stabilization time regardless of the
reset cause.
* The oscillation stabilization time for a power-on reset is fixed to 2
18
cycles of source oscillation. For other
types of reset, the oscillation stabilization wait time is determined by CS1 and CS0 of the clock selection
register.
As shown in Figure 4.2a, each reset cause has a corresponding flip-flop. The contents of the flip-flop can
be obtained by reading the watch-dog timer control register. If identifying the reset cause is required after
the reset is released, ensure that the value read from the watch-dog timer control register is processed by
software and processing branches to an appropriate program.
Table 4.2a Reset causes
Reset
Cause
Machine clock
Watch-dog timer
Oscillation
stabilization
wait
Power-on
When the power is turned
on
Main clock
Stop
Yes
Hardware
standby
’L’ level input to HSTX pin
Main clock
Stop
Yes
Watch-dog timer
Watch-dog timer overflow
Main clock
Stop
Yes
External pin
’L’ level input to RSTX pin
Previous status
maintained
Previous status
maintained
No
Software
’0’ written to RST bit of
STBYC
Previous status
maintained
Previous status
maintained
No