
5.3 Registers and register details
56
Chapter 5: Watchdog Timer, Timebase Timer, and Watch Timer Functions
MB90580 Series
5.3.2 TBTC (Time Base Timer Control Register)
Note:
Don’t use read-modify-write command to access this register, otherwise malfunction
will occur.
[bit 15] Reserved
This is a reserved bit. When writing data to this register, ensure that '1' is written to this bit.
[bit 12] TBIE
This bit is used to enable interval interrupts based on the time base timer. Writing '1' to this bit enables
interrupts, and writing '0' disables interrupts. This bit is initialized to '0' upon a reset. This bit is readable
and writable.
[bit 11] TBOF
This is an interrupt request flag for the time base timer. While the TBIE bit is '1,' an interrupt request is
issued when '1' is written to TBOF. This bit is set to '1' for each interval specified with the TBC1 and
TBC0 bits.
This bit is cleared by writing '0,' by switching to stop or hardware standby mode, or by a reset. Writing
'1' has no effect.
1' is always read by a read-modify-write instruction.
[bit 10] TBR
This bit clears all bits of the time base timer counter to '0.'
Writing '0' clears the time base counter.
Writing '1' has no effect.
'1' is always read from this bit.
Note:
Time base timer interrupt should be masked by either TBIE bit or ILM bit of CPU
before clearing the TBOF bit.
[bits 9 and 8] TBC1 and TBC0
These bits are used to set the time base timer interval.
Table 5.3.2a Selecting the time base timer interval
TBC1
TBC0
Interval at 4 MHz
source oscillation
Machine Clock Cycle
0
0
1.024 ms
2
12
cycle
0
1
4.096 ms
2
14
cycle
1
0
16.384 ms
2
16
cycle
1
1
131.072 ms
2
19
cycle
Address: 0000A9
H
Reserved
TBIE
TBOF
TBR
TBC1
TBC0
15
14
13
12
11
10
9
8
Bit number
(-)
(1)
(-)
(-)
(-)
(-)
(R/W)
(0)
(R/W)
(0)
(W)
(1)
(R/W)
(0)
(R/W)
(0)
Read/write
Initial value
Timer base timer control register
TBTC