
2.1 CPU
24
Chapter 2: CPU
MB90580 Series
I
Processor status (PS)
The PS register consists of the bits controlling the CPU Operation and the bits indicating the CPU status.
As shown in Figure 2.1.2g, the high-order byte of the PS register consists of a register bank pointer (RP) and
an interrupt level mask register (ILM). The RP indicates the start address of a register bank. The low-order
byte of the PS register is a condition code register (CCR), containing the flags to be set or reset depending on
the results of instruction execution or interruptoccurrences.
Figure 2.1.2g PS structure
(1)Condition code register (CCR)
Figure 2.1.2h Condition code register configuration
I:Interrupt enable flag:
Interrupts other than software interrupts are enabled when the I flag is 1
and are masked when the I flag is 0. The I flag is cleared by a reset.
S:Stack flag:
When the S flag is 0, USP is enabled as the stack manipulation pointer.
When the S flag is 1, SSP is enabled as the stack manipulation pointer.
The S flag is set by an interrupt reception or a reset.
T:Sticky bit flag:
1 is set in the T flag when there is at least one ’1’ in the data shifted out
from the carry after execution of a logical right/arithmetic right shift
instruction. Otherwise, 0 is set in the T flag. In addition, ’0’ is set in the T
flag when the shift amount is zero.
N:Negative flag:
The N flag is set when the MSB of the operation result is ’1,’ and is
otherwise cleared.
Z:Zero flag:
The Z flag is set when the operation result is all zeroes, and is otherwise
cleared.
V:Overflow flag:
The V flag is set when an overflow of a signed value occurs as a result of
operation execution and is otherwise cleared.
C:Carry flag:
The C flag is set when a carry-up or carry-down from the MSB occurs as
a result of operation execution and is otherwise cleared.
ILM
RP
CCR
PS
15
13 12
8 7
0
7
6
5
4
3
2
1
0
-
I
S
T
N
Z
V
C
: CCR
-
0
1
*
*
*
*
*
Initial value
*: Undefined