
12.3 Register and Register Details
130
Chapter 12: UART
MB90580 Series
12.3.3
Serial Input Data Register (SIDR0/1/2/3/4)/ Serial Ouput Data Register (SODR0/1/2/3/4)
These registers are data buffer registers for transmission and reception.
When a data item is seven bits long, the high-order one bit (D7) is invalid. To write a data item in the SODR
register, ensure that ’1’ is written to TDRE of the SSR register.
Note:
Writing a data item at this address means to write it to the SODR register. Reading this
address means to read the SIDR register.
12.3.4 Serial Status Register (SSR0/1/2/3/4)
The SSR register consists of the flags indicating the UART operation.
[bit 15] PE (Parity error)
This interrupt request flag is set when a parity error occurs during reception.
To clear a set flag, write ’0’ to the REC bit (bit 10) of the SCR register.
When this bit is set, the data in SIDR is invalid.
[bit 14] ORE (Overrun error):
This interrupt request flag is set when an overrun error occurs during reception.
To clear a set flag, write ’0’ to the REC bit (bit 10) of the SCR register.
When this bit is set, the data in SIDR is invalid.
0
No parity error has occurred.
[initial value]
1
A parity error has occurred.
0
No overrun error has occurred.
[initial value]
1
An overrun error has occurred.
D3
D2
D1
D0
D4
7
6
5
4
3
2
1
0
D5
D7
D6
Address : 000022
H
Serial input register/Serial output register
SIDR0/SODR0
SIDR1/SODR1
SIDR2/SODR2
SIDR3/SODR3
SIDR4/SODR4
000026
H
00002A
H
000084
H
Bit number
00008A
H
Read/write
(X)
(X)
(X)
(X)
(X)
(X)
(X)
(X)
Initial value
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
D3
D2
D1
D0
D4
7
6
5
4
3
2
1
0
D5
D7
D6
Address : 000022
H
Serial input register/Serial output register
SIDR0/SODR0
SIDR1/SODR1
SIDR2/SODR2
SIDR3/SODR3
SIDR4/SODR4
000026
H
00002A
H
000084
H
Bit number
00008A
H
Read/write
(X)
(X)
(X)
(X)
(X)
(X)
(X)
(X)
Initial value
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)