
45
MB86967
(7) DLCR6: Control Register 1
DLCR6 sets the MB86966 operation modes.
(Continued)
* : This register is accessible only for the device initialization.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Read/Write
ENA DLC
100NS/
150NS
SB/SW
BB/BW
TX BUF
SIZE 1
TX BUF
SIZE 0
BUF
SIZE 1
BUF
SIZE 0
Initial Value
10110110
Bit no.
Bit name
Operation
Value
Function
7ENA DLC
(Enable Data
Link Controller)
Read/Write
0
When 0 is written to this bit, the MB86967 is ready for
transmitting and receiving. When this bit is 0, the node ID
register and multicast address register cannot be accessed.
1
The data link controller and buffer manager in the MB86967
are initialized and both the transmitter and receiver buffers are
also initialized.
6
100NS/150NS
(SRAM Cycle
Time Select)
Read/Write
0
Sets cycle time of external SRAM to 150 ns
1
Sets cycle time of external SRAM to 100 ns.
In this case, use SRAM with an access time of 80 ns or less.
5SB/SW
(System Bus
Width Select)
Read/Write
—
Selects width of system data bus
PC Card Mode
When 1 is written to bit 5 (IOIS8) of the CCR1, the SB/-SW
bit is set to 1, placing the system data bus in the byte
transfer mode. When 0 is written, the SB/-SW bit is set to 0,
placing the system data bus in the word transfer mode.
In the PC card mode, writing to the SB/-SW bit is performed
by CCR1. Writing from DLCR6 does not affect bit 5.
General-purpose Bus Mode
The reversed value of the SB/SW bit is output to the
external pin SB/SW.
4BB/BW
(Buffer Memory
Bus Width)
Read
1
The width of the buffer memory data bus is fixed to 8 bits. The
read value of this bit is always 1.
Write
—
Not affected
3 and 2 TX BUF SIZE 1
TX BUF SIZE 0
(Transmitter
Buffer Size)
Read/Write
—
Sets size of transmitter buffer.
SB/SW
System Data Bus
0
16 bit
18 bit
TX BUF SIZE
Bank
Capacity
Bank
Count
Buffer
Capacity
10
0
2 Kbyte
1
2 Kbyte
0
1
2 Kbyte
2
4 Kbyte
1
0
4 Kbyte
2
8 Kbyte
1
8 Kbyte
2
16 Kbyte