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參數(shù)資料
| 型號(hào)： | MB86967PFV |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP100 |
| 封裝： | PLASTIC, LQFP-100 |
| 文件頁(yè)數(shù)： | 86/129頁(yè) |
| 文件大?。?/td> | 1519K |
| 代理商： | MB86967PFV |
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6
MB86967
s PIN DESCRIPTION
System interface pins in PC card mode
(Continued)
Pin no.
Symbol
Pin name
I/O
Function
18 to 23,
25,
27 to 29,
85,
87 to 91
PD0 to PD15
PC CARD DATA BUS
BD
PD15 for most significant bit and PD0 for least
significant bit. A built-in 150-k
pull-down resistor
eliminates the need for any resistor on the card.
4 to 14
PA0 to PA10
PC CARD ADDRESS
BUS
ID
PA10 for most significant bit and PA0 for least
significant bit. PA0 is invalid at word access. A built-in
150-k
pull-down resistor eliminates the need for any
resistor on the card.
82
CE1
CARD ENABLE 1,2
IU
CE1 controls even addresses and CE2 controls odd
addresses. At power-on or after reset-canceling,
these pins must be kept High for 20 ms to initialize
the I/O card.
83
CE2
96
OE
OUTPUT ENABLE
IU
This pin is used to control the output of read data
from attribute memory space.
95
WE
WRITE ENABLE
IU
This pin is used to control a write operation to
attribute memory space.
93
REG
REGISTER SELECT
IU
This pin must be kept Non-active High at access to
common memory. Keeping this pin Low accesses
attribute memory by OE/WE. The I/O area is
accessed by IORD/IOWE. Attribute memory is
allocated only to even addresses. Therefore, for word
access, data signals PD0 to PD7 are valid and PD8
to PD15 are invalid. Access to odd addresses is
disabled at byte access. When setting IORD/IOWE
Low during DMA operation, REG must be kept High
to prevent illegal access.
64
RESET1
HARDWARE RESET1
(Active High)
ISU This pin is used to clear the card configuration
register (CCR), set the card to an unset state (IC
card interface mode), and initialize the pointers and
registers in the LAN controller and 10BASE-T
transceiver. When power is applied to the card, the
system must keep this pin High or high-impedance
for 1 ms after the power supply has stabilized. A built-
in 150-k
pull-down resistor eliminates the need for
any resistor on the card.
63
RESET2
HARDWARE RESET2
(Active High)
ISD This pin is internally ORed with RESET1 and
contains a 50-k
pull-down resistor.
15
IORD
I/O READ
IU
This pin is used to read data from the I/O area. The
MB86967 sends no response to IORD until a write
operation to the CCR sets the card to the I/O card
interface mode.
17
IOWR
I/O WRITE
IU
This pin is used to write data to the I/O area. The
MB86967 sends no response to IOWR until a write
operation to the CCR sets the card to the I/O card
interface mode.
3WAIT
WAIT
O
A Low level is output to this pin to delay the end of an
I/O access cycle in progress.
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