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參數(shù)資料
| 型號： | MB86967PFV |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP100 |
| 封裝： | PLASTIC, LQFP-100 |
| 文件頁數(shù)： | 79/129頁 |
| 文件大?。?/td> | 1519K |
| 代理商： | MB86967PFV |
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53
MB86967
(6) BMPR14: Receiver Control/Transceiver Interrupt Enable/Shutdown Register
BMPR14 controls interrupts from the receiver buffer pointer and 10BASE-T transceiver.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Read
0
ENA LKF
INT
0
SHUT
DWN
MODE
TST3
SKIP RX
PKT
ENA
SQE INT
ENA
FILTER
Write
0
Initial Value
00000000
Bit no.
Bit name
Operation
Value
Function
7
Not used
Read/Write
—
The read value of this bit is always 0.
Always write 0 to this bit at writing.
6
ENA LKF INT
Read/Write
0
The link fail interrupt is disabled.
1
The link fail interrupt is enabled.
5
Not used
Read/Write
—
The read value of this bit is always 0.
Always write 0 to this bit at writing.
4
SHUT DWN
MODE
Read/Write
0
When bit 5 (STBY) of DLCR7 is set, the MB86967 enters the
standby state (oscillation continues).
1
When bit 5 (STBY) of DLCR7 is set, the MB86967 enters the
shutdown state (oscillation stops).
3
TST3 (Chip Test
3)
Read/Write
—
This a chip test bit. Always write 0 to this bit at writing to the
BMPR14. Writing 1 to this bit during normal operation is
prohibited.
2
SKIP RX PKT
Read/Write
0
Skipping the receiver buffer pointer is completed.
1
The receiver buffer pointer is being skipped (updated),
indicating the transient state from when 1 is written to this bit
until skipping the pointer is completed (about 200 ns).
0
Not affected.
The receiver buffer pointer is not skipped.
1
When 1 is written to this bit, the receiver buffer pointer is
skipped up to the beginning of the next packet. This bit is
cleared automatically when skipping is completed.
If the packet to be skipped is the last one in the receiver buffer,
the BUF EMP bit of DLCR5 is set after the receiver buffer
pointer is skipped.
This function works only after reading the receive packet
header (4 bytes). And, it is prohibited to write “1” when the
remainder of the packet becomes 8-byte.
1
ENA SQE INT
Read/Write
0
The signal quality error interrupt is disabled.
1
The signal quality error interrupt is enabled.
0FILTER SELF
RX
Read/Write
0
When the Address Match Mode bits AM1 and AM0 are 11, the
packet transmitted from the self office is also received.
1
When the Address Match Mode bits AM1 and AM0 are 11, the
packet transmitted from the self office is not received.
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