參數(shù)資料
型號: MB86967PFV
元件分類: 微控制器/微處理器
英文描述: 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP100
封裝: PLASTIC, LQFP-100
文件頁數(shù): 108/129頁
文件大小: 1519K
代理商: MB86967PFV
8
MB86967
System interface pins in ISA bus mode
(Continued)
Pin no.
Symbol
Pin name
I/O
Function
18 to 23,
25,
27 to 29,
85,
87 to 91
SD0 to SD15
SYSTEM DATA BUS
BD
These pins are used as data buses for data
exchange between the host system and the
MB86967. They are also used for DMA transfer. In
the 8-bit bus mode (bit 5 of DLCR6 = 1), only the 8
lower bits (SD0 to SD7) are used.
4 to 13
SA0 to SA9
SYSTEM ADDRESS
BUS
ID
These pins are used for input of system address
signals for selecting LAN controller registers.
64
CHRESET
CHIP RESET
(Active High)
ISU This pin is used for input of hardware reset signals.
15
IOR
I/O READ
(Active Low)
IU
This pin is used for input of I/O read strobe signals.
17
IOW
I/O WRITE
(Active Low)
IU
This pin is used for input of I/O write strobe signals.
63
AEN
ADDRESS ENABLE
(Active High)
ISD This pin is used for input of signals indicating that the
DMA controller controls the system bus.
65
EOP
END OF PROCESS
(Active High or Active
Low)
ID
This pin is used for input of signals indicating the end
of DMA transfer between the buffer memory and host
system. At input of EOP, the next BREQ is not output
and the handshaking cycle is terminated.
14
ALE
ADDRESS LATCH
ENABLE
ID
This pin is used for input of signals indicating that the
addresses of SA0 to SA9 are determined.
82
SBHE
SYSTEM BUS HIGH
ENABLE
IU
This pin is used for controlling byte/word transfer. In
the 16-bit data bus mode (bit 5 (SB/SW) of DLCR6 =
0), this pin, together with SA0, controls word transfer
and the transfer of upper and lower bytes on the data
bus.
×: don’t care
2DREQ
DMA REQUEST
(Active High)
O
This pin is used for output of DMA transfer request
signals.
SB/SW
SBHE
SA0
Function
0
Word transfer
00
1
Transfer of upper bytes on
data bus (SD15 to SD8)
01
0
Transfer of lower bytes on
data bus (SD7 to SD0)
01
1
Unused
1
××
Byte transfer
(SD7 to SD0)
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