參數(shù)資料
型號(hào)： MB86967PFV
元件分類： 微控制器/微處理器
英文描述： 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP100
封裝： PLASTIC, LQFP-100
文件頁數(shù)： 59/129頁
文件大?。?/td> 1519K
代理商： MB86967PFV
35
MB86967
s CONTROL REGISTERS IN LAN CONTROLLER
These control registers are used in all modes (PC card mode, ISA bus mode, and general-purpose bus mode).
The I/O address space between the base and 0 to F addresses has 32 control registers in the LAN controller
for two address-extended bits (RBS1 and RBS0). The two address-extended bits (RBS1 and RBS0) are at bits
3 and 2 of the control register DLCR7 in the LAN controller (base address +7).
Notes:1. At reset, the LAN controller defaults to the 8-bit system interface. However, in the PC card mode, the
8-bit or 16-bit interface is set by bit 5 (IOIS8) of CCR1 at switching from the IC memory interface to the
I/O card interface according to the CCR setting condition.
2. The PC card mode does not support DMA.
1. Arrangement of Registers
Register name
Symbol
System address
Register bank
SA3/PA3
SA2/PA2
SA1/PA1
SA0/PA0
RBS1
RBS0
Transmit status
DLCR0
0000
××
Receive status
DLCR1
0001
××
Transmit interrupt enable
DLCR2
0010
××
Receive interrupt enable
DLCR3
0011
××
Transmit mode
DLCR4
0100
××
Receive mode
DLCR5
0101
××
Control 1
DLCR6
0110
××
Control 2
DLCR7
0111
××
Node ID 0
DLCR8
100000
Node ID 1
DLCR9
100100
Node ID 2
DLCR10
101000
Node ID 3
DLCR11
101100
Node ID 4
DLCR12
110000
Node ID 5
DLCR13
110100
TDR0
DLCR14
111000
TDR1
DLCR15
111100
Multicast address 0
MAR8
100001
Multicast address 1
MAR9
100101
Multicast address 2
MAR10
101001
Multicast address 3
MAR11
101101
Multicast address 4
MAR12
110001
Multicast address 5
MAR13
110101
Multicast address 6
MAR14
111001
Multicast address 7
MAR15
111101
Buffer memory port
BMPR8
100010
Transmit packet count
BMPR10
101010
16 collision
BMPR11
101110
DMA enable
BMPR12
110010
DMA burst/transceiver mode
BMPR13
110110
Receive control/transceiver
interrupt
BMPR14
111010
Transceiver status/control
BMPR15
111110
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