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參數(shù)資料
| 型號： | M69030 |
| 元件分類： | 圖形處理器 |
| 英文描述： | GRAPHICS PROCESSOR, PBGA278 |
| 文件頁數(shù)： | 317/387頁 |
| 文件大?。?/td> | 2678K |
| 代理商： | M69030 |
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E-22
BitBLT Operation
`efmp69030 Databook
Revision 1.3 11/24/99
programming the BitBLT engine should begin by making sure that the BitBLT Configuration Register (XR20)
is set to 00h, to specify a color depth of 8 bits per pixel and to enable normal operation. Alternatively, if bit
23 of the BitBLT Control Register (BR04) is set to 1, then the color depth of the BitBLT engine may be set
to 8 bits per pixel by setting bits 25 and 24 of the same register to 0, although it is still necessary to ensure
that at least bit 1 of the BitBLT Configuration Register is set to 0 to enable normal operation.
The BitBLT Control Register (BR04) is used to select the features to be used in this BitBLT operation. Since
pattern data is not required for this operation, the BitBLT engine will ignore bits 22-17, however as a default,
these bits can be set to 0. Since monochrome source data will be used as the pixel mask for the per-pixel
write-masking operation used in this BitBLT operation, bits 16-14 must be set to 0, while bit 13 should be
set to 1. Bit 12 should be set to 1, to specify that the data source is monochrome. Bit 11 should be set to
0 to configure the BitBLT engine for a destination within the frame buffer. Bit 10 should be set to 1, to
indicate that the source data will be provided by the host CPU. Presuming that the host CPU will provide
the source data starting with the byte that carries the left-most pixel on the top-most scan line’s worth of the
source data, bits 9 and 8 should both be set to 0. Finally, bits 7-0 should be programmed with the 8-bit value
CCh to select the bit-wise logical operation that simply copies the source data to the destination. Selecting
this bit-wise operation in which no pattern data is used as an input, causes the BitBLT engine to
automatically forego reading pattern data from the frame buffer.
Unlike the earlier example of a pattern fill BitBLT operation where the Monochrome Source Control Register
(BR03) was entirely ignored, several features of this register will be used in this BitBLT operation. Bit 27 of
this register will be set to 0, thereby selecting the Pattern/Source Expansion Foreground Color Register
(BR02) to specify the color with which the letter “f” will be drawn. This example assumes that the source
data will be sent in one quadword that will be quadword-aligned. Therefore, bits 26, 25, and 24, which
specify alignment should be set to 1, 0, and 1, respectively. Since clipping will not be performed in this
BitBLT operation, bits 21-16, 13-8, and 5-0 should all be set to 0.
Bits 28-16 of the Source and Destination Offset Register (BR00) must be programmed with a value equal
to number of bytes in the interval between the first bytes of each adjacent scan line’s worth of destination
data. Since the color depth is 8 bits per pixel and the horizontal resolution of the display is 1024 pixels, the
value to be programmed into these bits is 400h, which is equal to the decimal value of 1024. Since the
source data used in this BitBLT operation is monochrome, the BitBLT engine will not use a byte-oriented
offset value for the source data. Therefore, bits 12-0 will be ignored.
Since the source data is monochrome, color expansion is required to convert it to color with a color depth
of 8 bits per pixel. Since the Pattern/Source Expansion Foreground Color Register (BR02) was selected to
specify the foreground color of black to be used in drawing the letter “f”, this register must be programmed
with the value for that color. With the graphics system set for a color depth of 8 bits per pixel, the actual
colors are specified in the RAMDAC palette, and the 8 bits stored in the frame buffer for each pixel actually
specify the index used to select a color from that palette. This example assumes that the color specified at
index 00h in the palette is black, and therefore bits 7-0 of this register should be set to 00h to select black
as the foreground color. The BitBLT engine ignores bits 23-8 of this register because the selected color
depth is 8 bits per pixel. Even though the color expansion being performed on the source data normally
requires that both the foreground and background colors be specified, the value used to specify the
background color is not important in this example. Per-pixel write-masking is being performed with the
monochrome source data as the pixel mask, which means that none of the pixels in the source data that will
be converted to the background color will ever be written to the destination. Since these pixels will never
be seen, the value programmed into the Pattern/Source Expansion Background Color Register (BR01) to
specify a background color is not important.
Since the CPU is providing the source data, and this source data is monochrome, the BitBLT engine ignores
all of bits 22-0 of the Source Address Register (BR06).
Bits 22-0 of the Destination Address Register (BR07) must be programmed with the address of the
destination data. This address is specified as an offset from the start of the frame buffer of the pixel at the
destination that will be written to first. In this case, the address is 20080h, which corresponds to the byte
representing the pixel at coordinates (128, 128).
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| M69032 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述: |
| M690SDM | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:SIGE SINGLE FREQUENCY VCSO |
| M690SDM-R01 | 功能描述:時鐘合成器/抖動清除器 VCSO RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| M690SDM-R02 | 功能描述:時鐘合成器/抖動清除器 VCSO RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| M690SDM-R03 | 功能描述:時鐘合成器/抖動清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
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