
CRT Controller Registers
9-9
`efmp69030 Databook
Revision 1.3 11/24/99
CR07
Overflow Register
read/write at I/O address 3B5h/3D5h with index at address 3B4h/3D4h set to 07h
shadowed for pipelines A and B
7
Vertical Sync Start Bit 9
The vertical sync start is a 10-bit or 12-bit value that specifies the beginning of the vertical
sync pulse relative to the beginning of the active display area.
In standard VGA modes, where bit 0 of the I/O Control Register (XR09) is set to 0, the
vertical sync start is specified with a 10-bit value. The 8 least significant bits of the vertical
sync start are supplied by bits 7-0 of the Vertical Sync Start Register (CR10), and the most
and second-most significant bits are supplied by bit 7 and bit 2 of this register (CR07),
respectively.
In extended modes, where bit 0 of the I/O Control Register (XR09) is set to 1, the vertical
display end is specified with a 12-bit value. The 8 least significant bits of the vertical display
end are supplied by bits 7-0 of the Vertical Sync Start Register (CR10), and the 4 most
significant bits are supplied by bits 3-0 of the Extended Vertical Sync Start Register (CR32)
register. In extended modes, neither bit 7 nor bit 2 of this register are used.
This 10-bit or 12-bit value should be programmed to be equal to the number of scanlines
from the beginning of the active display area to the start of the vertical sync pulse. Since
the active display area always starts on the 0th scanline, this number should be equal to
the number of the scanline on which the vertical sync pulse begins.
6
Vertical Display Enable End Bit 9
The vertical display enable end is a 10-bit or 12-bit value that specifies the number of the
last scanline within the active display area.
In standard VGA modes, where bit 0 of the I/O Control Register (XR09) is set to 0, the
vertical display enable end is specified with a 10-bit value. The 8 least significant bits of
the vertical display enable are supplied by bits 7-0 of the Vertical Display Enable End
Register (CR12), and the most and second-most significant bits are supplied by bit 6 and
bit 1 of this register (CR07), respectively.
In extended modes, where bit 0 of the I/O Control Register (XR09) is set to 1, the vertical
display enable end is specified with a 12-bit value. The 8 least significant bits of the vertical
display enable are supplied by bits 7-0 of the Vertical Display Enable End Register (CR12),
and the 4 most significant bits are supplied by bits 3-0 of the Extended Vertical Display End
Enable Register (CR31). In extended modes, neither bit 6 nor bit 1 of this register are used.
This 10-bit or 12-bit value should be programmed to be equal to the number of the last
scanline within in the active display area. Since the active display area always starts on
the 0th scanline, this number should be equal to the total number of scanlines within the
active display area minus 1.
76543
210
A
Vert Sync
Start Bit 9
Vert Disp En
Bit 9
Vert Total
Bit 9
Line Cmp Bit
8
Vert Blnk
Start Bit 8
Vert Sync
Start Bit 8
Vert Disp En
Bit 8
Vert Total
Bit 8
B
Vert Sync
Start Bit 9
Vert Disp En
Bit 9
Vert Total
Bit 9
Line Cmp Bit
8
Vert Blnk
Start Bit 8
Vert Sync
Start Bit 8
Vert Disp En
Bit 8
Vert Total
Bit 8