
Extension Registers
14-45
`efmp69030 Databook
Revision 1.3 11/24/99
XRC4
Dot Clock 1 VCO M-Divisor Register
read/write at I/O address 3D7h with index at I/O address 3D6h set to C4h
shared by both pipelines A and B
Note: All four of the registers used in specifying the loop parameters for dot clock 1 (XRC4 - XRC7) must
be written, and in order, from XRC4 to XRC7 before the hardware will update the synthesizer’s settings.
This is a form of double-buffering that is intended to prevent fluctuations in the synthesizer’s output as new
values are being written to these registers.
7-0
Dot Clock 1 VCO M-Divisor
This register the M-divisor, one of the loop parameters used in controlling the frequency of
the output of the synthesizer used to generate dot clock 1.
A series of calculations are used to derive this value and the values for the other loop
parameters given a desired output frequency and a series of constraints placed on different
components within the synthesizer used to generate dot clock 1. See appendix B for a
detailed description of the process used to derive the loop parameter values.
XRC5
Dot Clock 1 VCO N-Divisor Register
read/write at I/O address 3D7h with index at I/O address 3D6h set to C5h
shared by both pipelines A and B
Note: All four of the registers used in specifying the loop parameters for dot clock 1 (XRC4 - XRC7) must
be written, and in order from XRC4 to XRC7, before the hardware will update the synthesizer’s settings.
This is a form of double-buffering that is intended to prevent fluctuations in the synthesizer’s output as new
values are being written to these registers.
7-0
Dot Clock 1 VCO N-Divisor Bits 7-0
This register provides the N-divisor, one of the loop parameters used in controlling the
frequency of the output of the synthesizer used to generate dot clock 1.
A series of calculations are used to derive this value and the values for the other loop
parameters given a desired output frequency and a series of constraints placed on different
components within the synthesizer used to generate dot clock 1. See appendix B for a
detailed description of the process used to derive the loop parameter values.
76543
210
A
&
B
Dot Clock 1 VCO M-Divisor
7
6
5
4
32
10
A
&
B
Dot Clock 1 VCO N-Divisor Bits 7-0