
M44C892
M44C092
Rev. A5, 14-Dec-01
70 (84)
Combination mode 12: Burst modulation 2
SSI mode 1:
8-bit shift register internal data output (SO) to the Timer 3
Timer 2 output mode 2:
8-bit compare counter and 4-bit prescaler
Timer 2 output mode 1/6: Timer 2 compare match toggles (TOG2) to the SSI
Timer 3 mode 7:
Carrier frequency burst modulation controlled by the internal output (SO) of SSI
The Timer 3 counter is driven by an internal or external clock source. Its compare- and compare mode registers must
be programmed to generate the carrier frequency with the output toggle flip-flop (M3). The internal data output (SO)
of the SSI is used to enable and disable the Timer 3 output. The SSI can by supplied with the toggle signal of Timer 2.
01 0 123 450 1 0 1 2 3 4 50 1 0 1 2 345 010 1
5 010 1
5 01 0 1
5 0 1 0 1
30
1
2
3
0
1
3
2
CL3
Counter 3
CM31
CM32
TOG3
M3
Counter 2/2
TOG2
SO
T3O
13882
Figure 84. Burst modulation 2
Combination mode 13: FSK modulation
SSI mode 1:
8-bit shift register internal data output (SO) to the Timer 3
Timer 2 output mode 3:
8-bit compare counter and 4-bit prescaler
Timer 2 output mode 1/6: Timer 2 4-bit compare match signal (POUT) to the SSI
Timer 3 mode 8:
FSK modulation with shift register data output (SO)
The two compare registers are used to generate two different time intervals. The SSI data output selects which compare
register is used for the output frequency generation. A ’0’ level at the SSI data output enables the compare register 1
and an ’1’ level enables the compare register 2. The both compare- and compare mode registers must be programmed
to generate the two frequencies via the output toggle flip-flop. The SSI can be supplied with the toggle signal of Timer 2
or any other clock source. The Timer 3 counter is driven by an internal or external clock source.
01234012340123
Counter 3
CM31
CM32
SO
13815
401201201201201201201 20123
T3R
40
T3O
1
01
0
Figure 85. FSK modulation