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參數(shù)資料
| 型號(hào)： | M44C092 |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, 4 MHz, MICROCONTROLLER, PDSO20 |
| 封裝： | SSO-20 |
| 文件頁(yè)數(shù)： | 51/84頁(yè) |
| 文件大?。?/td> | 643K |
| 代理商： | M44C092 |
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M44C892
M44C892
M44C092
Rev. A5, 14-Dec-01
55 (84)
4 3210
76 54321 0
msb
lsb
rx data 1
rx data 2
rx data 3
msb
lsb
msb
lsb
Read SRB
(rx data 2)
Read SRB
(rx data 3)
Read SRB
(rx data 1)
SC
SD
SIR
SRDY
Interrupt
(IFN = 0)
Interrupt
(IFN = 1)
ACT
13825
765
43210
7 6 5
7654
Figure 61. Example of 8-bit synchronous receive operation
9-bit Shift Mode (I2C compatible)
In the 9-bit shift mode, the SSI is able to handle the I2C
protocol (described below). It always operates as an I2C
master device, i.e., SC is always generated and output by
the SSI. Both the I2C start and stop conditions are auto-
matically generated whenever the SSI is activated or
deactivated by the SIR–bit. In accordance with the I2C
protocol, the output data is always changed in the clock
low phase and shifted in on the high phase.
Before activating the SSI (SIR=0) and commencing an
I2C dialog, the appropriate data direction for the first
word must be set using the SDD control bit. The state of
this bit controls the direction of the data port (BP43 or
MCL_SD). Once started, the 8 data bits are, depending on
the selected direction, either clocked into or out of the
shift register. During the 9th clock period, the port
direction is automatically switched over so that the
corresponding acknowledge bit can be shifted out or read
in. In transmit mode, the acknowledge bit received from
the slave device is captured in the SSI Status Register
(TACK ) where it can be read by the controller. and in
receive mode, the state of the acknowledge bit to be
returned to the slave device is predetermined by the SSI
Status Register (RACK ).
Changing the directional mode (TX/RX) should not be
performed during the transfer of an I2C telegram. One
should wait until the end of the telegram which can be
detected using the SSI interrupt (IFN =1) or by
interrogating the ACT status.
A 9-bit telegram, once started will always run to
completion and will not be prematurely terminated by the
SIR bit. So, if the SIR–bit is set to ‘1’ in mit telegram, the
SSI will complete the current transfer and terminate the
dialog with an I2C stop condition.
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