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參數(shù)資料
| 型號： | M44C092 |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, 4 MHz, MICROCONTROLLER, PDSO20 |
| 封裝： | SSO-20 |
| 文件頁數(shù)： | 41/84頁 |
| 文件大?。?/td> | 643K |
| 代理商： | M44C092 |
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M44C892
M44C092
Rev. A5, 14-Dec-01
46 (84)
Timer 3 – Mode 10: Manchester demodulation / pulse-width demodulation
For Manchester demodulation, the edge detection stage must be programmed to detect each edge at the input. These
edges are evaluated by the demodulator stage. The timer stage is used to generate the shift clock for the SSI. The
compare register 1 match event defines the correct moment for shifting the state from the input T3I as the decoded bit
into shift register – after that the demodulator waits for the next edge to synchronize the timer by a reset for the next
bit. The compare register 2 can also be used to detect a time-out error and handle it with an interrupt routine (see also
combination mode 8).
10111
00
11
0
11
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
Synchronize
Manchester demodulation mode
Timer 3
mode
T3EX
SI
SR–DATA
13817
T3I
CM31=SCI
10
011
0
Figure 53. Manchester demodulation
Timer 3 – Mode 11: Biphase demodulation
In the Biphase demodulation mode, the timer operates like in Manchester demodulation mode. The difference is that
the bits are decoded via a toggle flip-flop. This flip-flop samples the edge in the middle of the bitframe and the compare
register 1 match event shifts the toggle flip-flop output into shift register (see also combined mode 9).
01
1
01
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
Synchronize
Biphase demodulation mode
Timer 3
mode
T3EX
Q1=SI
CM31=SCI
SR–DATA
13818
00
0
T3I
Reset
Counter 3
10101
0
Figure 54. Biphase demodulation
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