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參數(shù)資料
| 型號(hào)： | M44C092 |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, 4 MHz, MICROCONTROLLER, PDSO20 |
| 封裝： | SSO-20 |
| 文件頁(yè)數(shù)： | 56/84頁(yè) |
| 文件大?。?/td> | 643K |
| 代理商： | M44C092 |
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M44C892
M44C092
Rev. A5, 14-Dec-01
6 (84)
1
Introduction
The M44C092 / M44C892are members of Atmels family
of 4-bit single-chip microcontrollers. They contain ROM,
RAM, parallel I/O ports, two 8-bit programmable multi-
function timer/counters, voltage supervisor, interval
timer with watchdog function and a sophisticated on-chip
clock generation with integrated RC-, 32-kHz crystal-
and 4-MHz crystal-oscillators.
Table 2 provides an overview of the available variants.
Table 2 Available variants of M4xCx9x
Version
Type
ROM
E2PROM peripheral
Packages
Flash device
T48C893
4 Kbyte EEPROM
64 byte
SSO20
Production
M44C092
4 Kbyte mask ROM
–––
SSO20
Production
M44C892
4 Kbyte mask ROM
64 byte
SSO20
2
MARC4 Architecture
2.1
General Description
The MARC4 microcontroller consists of an advanced
stack-based, 4-bit CPU core and on-chip peripherals. The
CPU is based on the HARVARD architecture with
physically separate program memory (ROM) and data
memory
(RAM).
Three
independent
buses,
the
instruction bus, the memory bus and the I/O bus, are used
for parallel communication between ROM, RAM and
peripherals. This enhances program execution speed by
allowing both instruction prefetching, and a simultaneous
communication to the on-chip peripheral circuitry. The
extremely powerful integrated interrupt controller with
associated eight prioritized interrupt levels supports fast
and efficient processing of hardware events. The MARC4
is designed for the high-level programming language
qFORTH. The core includes both, an expression and a
return
stack.
This
architecture
enables
high-level
language programming without any loss of efficiency or
code density.
Instruction
decoder
CCR
TOS
ALU
RAM
PC
RP
SP
X
Y
Program
256 x 4-bit
MARC4 CORE
Clock
Reset
Sleep
Memory bus
I/O bus
Instruction
bus
Reset
System
clock
Interrupt
controller
On–chip peripheral modules
94 8973
memory
Figure 3. MARC4 core
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